forked from luck/tmp_suning_uos_patched
7cc4e87f91
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
[ARM] 5300/1: fixup spitz reset during boot
[ARM] 5295/1: make ZONE_DMA optional
[ARM] 5239/1: Palm Zire 72 power management support
[ARM] 5298/1: Drop desc_handle_irq()
[ARM] 5297/1: [KS8695] Fix two compile-time warnings
[ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
[ARM] pxa: allow multi-machine PCMCIA builds
[ARM] pxa: add preliminary CPUFREQ support for PXA3xx
[ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
[ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
[ARM] pxa/zylonite: add support for USB OHCI
[ARM] ohci-pxa27x: use ioremap() and offset for register access
[ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
[ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
[ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
[ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
[ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
[ARM] pxa: simplify DMA register definitions
[ARM] pxa: make additional DCSR bits valid for PXA3xx
[ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
...
Fixed up conflicts in
arch/arm/mach-versatile/core.c
sound/soc/pxa/pxa2xx-ac97.c
sound/soc/pxa/pxa2xx-i2s.c
manually.
138 lines
4.0 KiB
C
138 lines
4.0 KiB
C
/*
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* TI DaVinci Power and Sleep Controller (PSC)
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/psc.h>
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#include <mach/mux.h>
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/* PSC register offsets */
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#define EPCPR 0x070
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#define PTCMD 0x120
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#define PTSTAT 0x128
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#define PDSTAT 0x200
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#define PDCTL1 0x304
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#define MDSTAT 0x800
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#define MDCTL 0xA00
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/* System control register offsets */
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#define VDD3P3V_PWDN 0x48
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static void davinci_psc_mux(unsigned int id)
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{
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switch (id) {
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case DAVINCI_LPSC_ATA:
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davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1);
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davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1);
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break;
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case DAVINCI_LPSC_MMC_SD:
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/* VDD power manupulations are done in U-Boot for CPMAC
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* so applies to MMC as well
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*/
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/*Set up the pull regiter for MMC */
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davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN);
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davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0);
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break;
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case DAVINCI_LPSC_I2C:
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davinci_mux_peripheral(DAVINCI_MUX_I2C, 1);
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break;
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case DAVINCI_LPSC_McBSP:
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davinci_mux_peripheral(DAVINCI_MUX_ASP, 1);
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break;
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default:
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break;
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}
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}
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/* Enable or disable a PSC domain */
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void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
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{
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u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
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mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
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if (enable)
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mdctl |= 0x00000003; /* Enable Module */
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else
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mdctl &= 0xFFFFFFF2; /* Disable Module */
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davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
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pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT);
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if ((pdstat & 0x00000001) == 0) {
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pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
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pdctl1 |= 0x1;
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davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
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ptcmd = 1 << domain;
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davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
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do {
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epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
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EPCPR);
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} while ((((epcpr >> domain) & 1) == 0));
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pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
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pdctl1 |= 0x100;
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davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
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do {
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ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
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PTSTAT);
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} while (!(((ptstat >> domain) & 1) == 0));
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} else {
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ptcmd = 1 << domain;
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davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
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do {
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ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
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PTSTAT);
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} while (!(((ptstat >> domain) & 1) == 0));
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}
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if (enable)
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mdstat_mask = 0x3;
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else
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mdstat_mask = 0x2;
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do {
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mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
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MDSTAT + 4 * id);
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} while (!((mdstat & 0x0000001F) == mdstat_mask));
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if (enable)
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davinci_psc_mux(id);
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}
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void __init davinci_psc_init(void)
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{
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davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSMSTR, 1);
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davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSSLV, 1);
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davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1);
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davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC0, 1);
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davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC1, 1);
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davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_GPIO, 1);
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/* Turn on WatchDog timer LPSC. Needed for RESET to work */
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davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TIMER2, 1);
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}
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