forked from luck/tmp_suning_uos_patched
da181a8b39
Add the three bare TLB accessor functions to paravirt-ops. Most amusingly, flush_tlb is redefined on SMP, so I can't call the paravirt op flush_tlb. Instead, I chose to indicate the actual flush type, kernel (global) vs. user (non-global). Global in this sense means using the global bit in the page table entry, which makes TLB entries persistent across CR3 reloads, not global as in the SMP sense of invoking remote shootdowns, so the term is confusingly overloaded. AK: folded in fix from Zach for PAE compilation Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Chris Wright <chrisw@sous-sol.org> Signed-off-by: Andi Kleen <ak@suse.de> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by: Andrew Morton <akpm@osdl.org>
155 lines
3.9 KiB
C
155 lines
3.9 KiB
C
#ifndef _I386_TLBFLUSH_H
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#define _I386_TLBFLUSH_H
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#include <linux/mm.h>
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#include <asm/processor.h>
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define __flush_tlb() __native_flush_tlb()
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#define __flush_tlb_global() __native_flush_tlb_global()
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#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
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#endif
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#define __native_flush_tlb() \
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do { \
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unsigned int tmpreg; \
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\
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__asm__ __volatile__( \
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"movl %%cr3, %0; \n" \
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"movl %0, %%cr3; # flush TLB \n" \
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: "=r" (tmpreg) \
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:: "memory"); \
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} while (0)
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/*
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* Global pages have to be flushed a bit differently. Not a real
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* performance problem because this does not happen often.
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*/
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#define __native_flush_tlb_global() \
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do { \
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unsigned int tmpreg, cr4, cr4_orig; \
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\
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__asm__ __volatile__( \
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"movl %%cr4, %2; # turn off PGE \n" \
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"movl %2, %1; \n" \
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"andl %3, %1; \n" \
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"movl %1, %%cr4; \n" \
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"movl %%cr3, %0; \n" \
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"movl %0, %%cr3; # flush TLB \n" \
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"movl %2, %%cr4; # turn PGE back on \n" \
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: "=&r" (tmpreg), "=&r" (cr4), "=&r" (cr4_orig) \
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: "i" (~X86_CR4_PGE) \
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: "memory"); \
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} while (0)
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#define __native_flush_tlb_single(addr) \
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__asm__ __volatile__("invlpg (%0)" ::"r" (addr) : "memory")
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# define __flush_tlb_all() \
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do { \
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if (cpu_has_pge) \
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__flush_tlb_global(); \
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else \
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__flush_tlb(); \
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} while (0)
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#define cpu_has_invlpg (boot_cpu_data.x86 > 3)
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#ifdef CONFIG_X86_INVLPG
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# define __flush_tlb_one(addr) __flush_tlb_single(addr)
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#else
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# define __flush_tlb_one(addr) \
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do { \
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if (cpu_has_invlpg) \
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__flush_tlb_single(addr); \
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else \
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__flush_tlb(); \
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} while (0)
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#endif
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/*
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* TLB flushing:
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*
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* - flush_tlb() flushes the current mm struct TLBs
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* - flush_tlb_all() flushes all processes TLBs
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
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*
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* ..but the i386 has somewhat limited tlb flushing capabilities,
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* and page-granular flushes are available only on i486 and up.
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*/
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#ifndef CONFIG_SMP
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#define flush_tlb() __flush_tlb()
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#define flush_tlb_all() __flush_tlb_all()
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#define local_flush_tlb() __flush_tlb()
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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if (mm == current->active_mm)
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__flush_tlb();
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long addr)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb_one(addr);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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if (vma->vm_mm == current->active_mm)
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__flush_tlb();
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}
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#else
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#include <asm/smp.h>
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#define local_flush_tlb() \
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__flush_tlb()
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extern void flush_tlb_all(void);
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extern void flush_tlb_current_task(void);
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extern void flush_tlb_mm(struct mm_struct *);
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extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
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#define flush_tlb() flush_tlb_current_task()
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static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
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{
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flush_tlb_mm(vma->vm_mm);
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}
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#define TLBSTATE_OK 1
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#define TLBSTATE_LAZY 2
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struct tlb_state
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{
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struct mm_struct *active_mm;
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int state;
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char __cacheline_padding[L1_CACHE_BYTES-8];
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};
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DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate);
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#endif
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#define flush_tlb_kernel_range(start, end) flush_tlb_all()
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static inline void flush_tlb_pgtables(struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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/* i386 does not keep any page table caches in TLB */
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}
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#endif /* _I386_TLBFLUSH_H */
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