forked from luck/tmp_suning_uos_patched
7888bc2b47
The calculation to get TI_CPU based off of SPRG3 was just plain wrong, meaning that we were getting garbage for the CPU number on 6xx/G3/G4 based SMP boxes in this code. Just offset off the stack pointer (to get to thread_info) like all the other references to TI_CPU do. This was pointed out by Chen Gong <G.Chen@freescale.com> [paulus@samba.org - use rlwinm r12,r11,... instead of rlwinm r12,r1,...; tophys()] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
95 lines
2.2 KiB
ArmAsm
95 lines
2.2 KiB
ArmAsm
/*
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* Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved.
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* Dave Liu <daveliu@freescale.com>
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* copy from idle_6xx.S and modify for e500 based processor,
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* implement the power_save function in idle.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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.text
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_GLOBAL(e500_idle)
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rlwinm r3,r1,0,0,31-THREAD_SHIFT /* current thread_info */
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lwz r4,TI_LOCAL_FLAGS(r3) /* set napping bit */
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ori r4,r4,_TLF_NAPPING /* so when we take an exception */
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stw r4,TI_LOCAL_FLAGS(r3) /* it will return to our caller */
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/* Check if we can nap or doze, put HID0 mask in r3 */
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lis r3,0
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BEGIN_FTR_SECTION
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lis r3,HID0_DOZE@h
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
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BEGIN_FTR_SECTION
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/* Now check if user enabled NAP mode */
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lis r4,powersave_nap@ha
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lwz r4,powersave_nap@l(r4)
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cmpwi 0,r4,0
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beq 1f
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stwu r1,-16(r1)
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mflr r0
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stw r0,20(r1)
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bl flush_dcache_L1
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lwz r0,20(r1)
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addi r1,r1,16
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mtlr r0
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lis r3,HID0_NAP@h
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
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BEGIN_FTR_SECTION
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msync
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li r7,L2CSR0_L2FL@l
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mtspr SPRN_L2CSR0,r7
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2:
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mfspr r7,SPRN_L2CSR0
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andi. r4,r7,L2CSR0_L2FL@l
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bne 2b
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END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP)
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1:
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/* Go to NAP or DOZE now */
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mfspr r4,SPRN_HID0
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rlwinm r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP)
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or r4,r4,r3
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isync
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mtspr SPRN_HID0,r4
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isync
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mfmsr r7
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oris r7,r7,MSR_WE@h
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ori r7,r7,MSR_EE
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msync
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mtmsr r7
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isync
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2: b 2b
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/*
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* Return from NAP/DOZE mode, restore some CPU specific registers,
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* r2 containing physical address of current.
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* r11 points to the exception frame (physical address).
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* We have to preserve r10.
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*/
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_GLOBAL(power_save_ppc32_restore)
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lwz r9,_LINK(r11) /* interrupted in e500_idle */
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stw r9,_NIP(r11) /* make it do a blr */
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#ifdef CONFIG_SMP
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rlwinm r12,r1,0,0,31-THREAD_SHIFT
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lwz r11,TI_CPU(r12) /* get cpu number * 4 */
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slwi r11,r11,2
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#else
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li r11,0
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#endif
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b transfer_to_handler_cont
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