forked from luck/tmp_suning_uos_patched
a7ba70f178
Using a mask to represent bus DMA constraints has a set of limitations. The biggest one being it can only hold a power of two (minus one). The DMA mapping code is already aware of this and treats dev->bus_dma_mask as a limit. This quirk is already used by some architectures although still rare. With the introduction of the Raspberry Pi 4 we've found a new contender for the use of bus DMA limits, as its PCIe bus can only address the lower 3GB of memory (of a total of 4GB). This is impossible to represent with a mask. To make things worse the device-tree code rounds non power of two bus DMA limits to the next power of two, which is unacceptable in this case. In the light of this, rename dev->bus_dma_mask to dev->bus_dma_limit all over the tree and treat it as such. Note that dev->bus_dma_limit should contain the higher accessible DMA address. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2004, 2006 MIPS Technologies, Inc. All rights reserved.
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* Author: Maciej W. Rozycki <macro@mips.com>
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* Copyright (C) 2018 Maciej W. Rozycki
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*/
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#include <linux/dma-mapping.h>
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#include <linux/pci.h>
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/*
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* Set the BCM1250, etc. PCI host bridge's TRDY timeout
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* to the finite max.
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*/
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static void quirk_sb1250_pci(struct pci_dev *dev)
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{
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pci_write_config_byte(dev, 0x40, 0xff);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
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quirk_sb1250_pci);
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/*
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* The BCM1250, etc. PCI host bridge does not support DAC on its 32-bit
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* bus, so we set the bus's DMA limit accordingly. However the HT link
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* down the artificial PCI-HT bridge supports 40-bit addressing and the
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* SP1011 HT-PCI bridge downstream supports both DAC and a 64-bit bus
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* width, so we record the PCI-HT bridge's secondary and subordinate bus
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* numbers and do not set the limit for devices present in the inclusive
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* range of those.
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*/
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struct sb1250_bus_dma_limit_exclude {
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bool set;
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unsigned char start;
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unsigned char end;
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};
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static int sb1250_bus_dma_limit(struct pci_dev *dev, void *data)
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{
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struct sb1250_bus_dma_limit_exclude *exclude = data;
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bool exclude_this;
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bool ht_bridge;
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exclude_this = exclude->set && (dev->bus->number >= exclude->start &&
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dev->bus->number <= exclude->end);
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ht_bridge = !exclude->set && (dev->vendor == PCI_VENDOR_ID_SIBYTE &&
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dev->device == PCI_DEVICE_ID_BCM1250_HT);
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if (exclude_this) {
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dev_dbg(&dev->dev, "not disabling DAC for device");
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} else if (ht_bridge) {
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exclude->start = dev->subordinate->number;
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exclude->end = pci_bus_max_busnr(dev->subordinate);
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exclude->set = true;
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dev_dbg(&dev->dev, "not disabling DAC for [bus %02x-%02x]",
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exclude->start, exclude->end);
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} else {
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dev_dbg(&dev->dev, "disabling DAC for device");
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dev->dev.bus_dma_limit = DMA_BIT_MASK(32);
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}
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return 0;
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}
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static void quirk_sb1250_pci_dac(struct pci_dev *dev)
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{
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struct sb1250_bus_dma_limit_exclude exclude = { .set = false };
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pci_walk_bus(dev->bus, sb1250_bus_dma_limit, &exclude);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
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quirk_sb1250_pci_dac);
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/*
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* The BCM1250, etc. PCI/HT bridge reports as a host bridge.
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*/
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static void quirk_sb1250_ht(struct pci_dev *dev)
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{
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dev->class = PCI_CLASS_BRIDGE_PCI << 8;
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT,
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quirk_sb1250_ht);
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/*
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* Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max.
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*/
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static void quirk_sp1011(struct pci_dev *dev)
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{
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pci_write_config_byte(dev, 0x64, 0xff);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIPACKETS, PCI_DEVICE_ID_SP1011,
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quirk_sp1011);
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