forked from luck/tmp_suning_uos_patched
a1f6e0211b
Description:
1. Implement PCI-Express error recovery function and AER
capability, especially thanks to Yanmin Zhang's openhanded help
about AER
2. Implement the selection of ARCMSR_MAX_XFER_SECTORS_B=4096 if
firmware version is latter than 1.42
3. Add arcmsr_done4_abort_postqueue in arcmsr_iop_reset function
to improve the stability as hot-unplug/plug
4. Modify the ISR, arcmsr_interrupt routine, to prevent the
inconsistency with sg_mod driver if application directly calls
the arcmsr driver w/o passing through scsi midlayer
Signed-off-by: Nick Cheng <nick.cheng@areca.com.tw>
[jejb: unused variable removal]
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
473 lines
18 KiB
C
473 lines
18 KiB
C
/*
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*******************************************************************************
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** O.S : Linux
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** FILE NAME : arcmsr.h
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** BY : Erich Chen
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** Description: SCSI RAID Device Driver for
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** ARECA RAID Host adapter
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*******************************************************************************
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** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
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**
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** Web site: www.areca.com.tw
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** E-mail: erich@areca.com.tw
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License version 2 as
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** published by the Free Software Foundation.
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** This program is distributed in the hope that it will be useful,
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** but WITHOUT ANY WARRANTY; without even the implied warranty of
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** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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** GNU General Public License for more details.
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*******************************************************************************
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** Redistribution and use in source and binary forms, with or without
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** modification, are permitted provided that the following conditions
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** are met:
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** 1. Redistributions of source code must retain the above copyright
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** notice, this list of conditions and the following disclaimer.
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** 2. Redistributions in binary form must reproduce the above copyright
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** notice, this list of conditions and the following disclaimer in the
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** documentation and/or other materials provided with the distribution.
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** 3. The name of the author may not be used to endorse or promote products
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** derived from this software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
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** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
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** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
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** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#include <linux/interrupt.h>
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struct class_device_attribute;
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#define ARCMSR_MAX_OUTSTANDING_CMD 256
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#define ARCMSR_MAX_FREECCB_NUM 288
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#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.14"
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#define ARCMSR_SCSI_INITIATOR_ID 255
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#define ARCMSR_MAX_XFER_SECTORS 512
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#define ARCMSR_MAX_XFER_SECTORS_B 4096
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#define ARCMSR_MAX_TARGETID 17
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#define ARCMSR_MAX_TARGETLUN 8
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#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
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#define ARCMSR_MAX_QBUFFER 4096
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#define ARCMSR_MAX_SG_ENTRIES 38
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/*
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*******************************************************************************
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** split 64bits dma addressing
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*******************************************************************************
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*/
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#define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
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#define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
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/*
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*******************************************************************************
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** MESSAGE CONTROL CODE
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*******************************************************************************
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*/
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struct CMD_MESSAGE
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{
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uint32_t HeaderLength;
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uint8_t Signature[8];
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uint32_t Timeout;
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uint32_t ControlCode;
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uint32_t ReturnCode;
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uint32_t Length;
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};
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/*
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*******************************************************************************
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** IOP Message Transfer Data for user space
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*******************************************************************************
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*/
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struct CMD_MESSAGE_FIELD
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{
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struct CMD_MESSAGE cmdmessage;
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uint8_t messagedatabuffer[1032];
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};
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/* IOP message transfer */
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#define ARCMSR_MESSAGE_FAIL 0x0001
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/* DeviceType */
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#define ARECA_SATA_RAID 0x90000000
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/* FunctionCode */
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#define FUNCTION_READ_RQBUFFER 0x0801
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#define FUNCTION_WRITE_WQBUFFER 0x0802
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#define FUNCTION_CLEAR_RQBUFFER 0x0803
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#define FUNCTION_CLEAR_WQBUFFER 0x0804
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#define FUNCTION_CLEAR_ALLQBUFFER 0x0805
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#define FUNCTION_RETURN_CODE_3F 0x0806
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#define FUNCTION_SAY_HELLO 0x0807
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#define FUNCTION_SAY_GOODBYE 0x0808
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#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
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/* ARECA IO CONTROL CODE*/
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#define ARCMSR_MESSAGE_READ_RQBUFFER \
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ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER
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#define ARCMSR_MESSAGE_WRITE_WQBUFFER \
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ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER
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#define ARCMSR_MESSAGE_CLEAR_RQBUFFER \
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ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER
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#define ARCMSR_MESSAGE_CLEAR_WQBUFFER \
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ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER
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#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \
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ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER
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#define ARCMSR_MESSAGE_RETURN_CODE_3F \
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ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F
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#define ARCMSR_MESSAGE_SAY_HELLO \
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ARECA_SATA_RAID | FUNCTION_SAY_HELLO
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#define ARCMSR_MESSAGE_SAY_GOODBYE \
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ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE
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#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \
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ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
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/* ARECA IOCTL ReturnCode */
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#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
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#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
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#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
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/*
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*************************************************************
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** structure for holding DMA address data
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*************************************************************
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*/
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#define IS_SG64_ADDR 0x01000000 /* bit24 */
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struct SG32ENTRY
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{
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uint32_t length;
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uint32_t address;
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};
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struct SG64ENTRY
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{
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uint32_t length;
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uint32_t address;
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uint32_t addresshigh;
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};
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struct SGENTRY_UNION
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{
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union
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{
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struct SG32ENTRY sg32entry;
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struct SG64ENTRY sg64entry;
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}u;
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};
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/*
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********************************************************************
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** Q Buffer of IOP Message Transfer
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********************************************************************
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*/
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struct QBUFFER
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{
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uint32_t data_len;
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uint8_t data[124];
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};
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/*
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*******************************************************************************
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** FIRMWARE INFO
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*******************************************************************************
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*/
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struct FIRMWARE_INFO
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{
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uint32_t signature; /*0, 00-03*/
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uint32_t request_len; /*1, 04-07*/
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uint32_t numbers_queue; /*2, 08-11*/
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uint32_t sdram_size; /*3, 12-15*/
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uint32_t ide_channels; /*4, 16-19*/
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char vendor[40]; /*5, 20-59*/
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char model[8]; /*15, 60-67*/
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char firmware_ver[16]; /*17, 68-83*/
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char device_map[16]; /*21, 84-99*/
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};
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/* signature of set and get firmware config */
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#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
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#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
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/* message code of inbound message register */
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#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
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#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
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#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
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#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
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#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
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#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
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#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
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#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
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#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
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/* doorbell interrupt generator */
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#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
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#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
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#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
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#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
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/* ccb areca cdb flag */
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#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
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#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
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#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
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#define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000
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/* outbound firmware ok */
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#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
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/*
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*******************************************************************************
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** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
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*******************************************************************************
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*/
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struct ARCMSR_CDB
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{
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uint8_t Bus;
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uint8_t TargetID;
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uint8_t LUN;
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uint8_t Function;
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uint8_t CdbLength;
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uint8_t sgcount;
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uint8_t Flags;
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#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01
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#define ARCMSR_CDB_FLAG_BIOS 0x02
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#define ARCMSR_CDB_FLAG_WRITE 0x04
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#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
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#define ARCMSR_CDB_FLAG_HEADQ 0x08
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#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
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uint8_t Reserved1;
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uint32_t Context;
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uint32_t DataLength;
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uint8_t Cdb[16];
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uint8_t DeviceStatus;
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#define ARCMSR_DEV_CHECK_CONDITION 0x02
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#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
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#define ARCMSR_DEV_ABORTED 0xF1
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#define ARCMSR_DEV_INIT_FAIL 0xF2
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uint8_t SenseData[15];
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union
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{
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struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES];
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struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES];
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} u;
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};
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/*
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*******************************************************************************
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** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331)
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*******************************************************************************
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*/
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struct MessageUnit
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{
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uint32_t resrved0[4]; /*0000 000F*/
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uint32_t inbound_msgaddr0; /*0010 0013*/
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uint32_t inbound_msgaddr1; /*0014 0017*/
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uint32_t outbound_msgaddr0; /*0018 001B*/
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uint32_t outbound_msgaddr1; /*001C 001F*/
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uint32_t inbound_doorbell; /*0020 0023*/
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uint32_t inbound_intstatus; /*0024 0027*/
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uint32_t inbound_intmask; /*0028 002B*/
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uint32_t outbound_doorbell; /*002C 002F*/
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uint32_t outbound_intstatus; /*0030 0033*/
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uint32_t outbound_intmask; /*0034 0037*/
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uint32_t reserved1[2]; /*0038 003F*/
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uint32_t inbound_queueport; /*0040 0043*/
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uint32_t outbound_queueport; /*0044 0047*/
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uint32_t reserved2[2]; /*0048 004F*/
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uint32_t reserved3[492]; /*0050 07FF 492*/
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uint32_t reserved4[128]; /*0800 09FF 128*/
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uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/
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uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/
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uint32_t reserved5[32]; /*0E80 0EFF 32*/
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uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
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uint32_t reserved6[32]; /*0F80 0FFF 32*/
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};
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/*
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*******************************************************************************
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** Adapter Control Block
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*******************************************************************************
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*/
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struct AdapterControlBlock
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{
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struct pci_dev * pdev;
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struct Scsi_Host * host;
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unsigned long vir2phy_offset;
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/* Offset is used in making arc cdb physical to virtual calculations */
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uint32_t outbound_int_enable;
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struct MessageUnit __iomem * pmu;
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/* message unit ATU inbound base address0 */
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uint32_t acb_flags;
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#define ACB_F_SCSISTOPADAPTER 0x0001
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#define ACB_F_MSG_STOP_BGRB 0x0002
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/* stop RAID background rebuild */
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#define ACB_F_MSG_START_BGRB 0x0004
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/* stop RAID background rebuild */
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#define ACB_F_IOPDATA_OVERFLOW 0x0008
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/* iop message data rqbuffer overflow */
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#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
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/* message clear wqbuffer */
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#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
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/* message clear rqbuffer */
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#define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
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#define ACB_F_BUS_RESET 0x0080
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#define ACB_F_IOP_INITED 0x0100
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/* iop init */
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struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
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/* used for memory free */
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struct list_head ccb_free_list;
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/* head of free ccb list */
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atomic_t ccboutstandingcount;
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void * dma_coherent;
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/* dma_coherent used for memory free */
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dma_addr_t dma_coherent_handle;
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/* dma_coherent_handle used for memory free */
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uint8_t rqbuffer[ARCMSR_MAX_QBUFFER];
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/* data collection buffer for read from 80331 */
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int32_t rqbuf_firstindex;
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/* first of read buffer */
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int32_t rqbuf_lastindex;
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/* last of read buffer */
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uint8_t wqbuffer[ARCMSR_MAX_QBUFFER];
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/* data collection buffer for write to 80331 */
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int32_t wqbuf_firstindex;
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/* first of write buffer */
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int32_t wqbuf_lastindex;
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/* last of write buffer */
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uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
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/* id0 ..... id15, lun0...lun7 */
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#define ARECA_RAID_GONE 0x55
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#define ARECA_RAID_GOOD 0xaa
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uint32_t num_resets;
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uint32_t num_aborts;
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uint32_t firm_request_len;
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uint32_t firm_numbers_queue;
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uint32_t firm_sdram_size;
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uint32_t firm_hd_channels;
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char firm_model[12];
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char firm_version[20];
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};/* HW_DEVICE_EXTENSION */
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/*
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*******************************************************************************
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** Command Control Block
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** this CCB length must be 32 bytes boundary
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*******************************************************************************
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*/
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struct CommandControlBlock
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{
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struct ARCMSR_CDB arcmsr_cdb;
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/*
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** 0-503 (size of CDB=504):
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** arcmsr messenger scsi command descriptor size 504 bytes
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*/
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uint32_t cdb_shifted_phyaddr;
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/* 504-507 */
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uint32_t reserved1;
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/* 508-511 */
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#if BITS_PER_LONG == 64
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/* ======================512+64 bytes======================== */
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struct list_head list;
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/* 512-527 16 bytes next/prev ptrs for ccb lists */
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struct scsi_cmnd * pcmd;
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/* 528-535 8 bytes pointer of linux scsi command */
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struct AdapterControlBlock * acb;
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/* 536-543 8 bytes pointer of acb */
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uint16_t ccb_flags;
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/* 544-545 */
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#define CCB_FLAG_READ 0x0000
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#define CCB_FLAG_WRITE 0x0001
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#define CCB_FLAG_ERROR 0x0002
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#define CCB_FLAG_FLUSHCACHE 0x0004
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#define CCB_FLAG_MASTER_ABORTED 0x0008
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uint16_t startdone;
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/* 546-547 */
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#define ARCMSR_CCB_DONE 0x0000
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#define ARCMSR_CCB_START 0x55AA
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#define ARCMSR_CCB_ABORTED 0xAA55
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#define ARCMSR_CCB_ILLEGAL 0xFFFF
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uint32_t reserved2[7];
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/* 548-551 552-555 556-559 560-563 564-567 568-571 572-575 */
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#else
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/* ======================512+32 bytes======================== */
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struct list_head list;
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/* 512-519 8 bytes next/prev ptrs for ccb lists */
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struct scsi_cmnd * pcmd;
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/* 520-523 4 bytes pointer of linux scsi command */
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struct AdapterControlBlock * acb;
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/* 524-527 4 bytes pointer of acb */
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uint16_t ccb_flags;
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/* 528-529 */
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#define CCB_FLAG_READ 0x0000
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#define CCB_FLAG_WRITE 0x0001
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#define CCB_FLAG_ERROR 0x0002
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#define CCB_FLAG_FLUSHCACHE 0x0004
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#define CCB_FLAG_MASTER_ABORTED 0x0008
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uint16_t startdone;
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/* 530-531 */
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#define ARCMSR_CCB_DONE 0x0000
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#define ARCMSR_CCB_START 0x55AA
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#define ARCMSR_CCB_ABORTED 0xAA55
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#define ARCMSR_CCB_ILLEGAL 0xFFFF
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uint32_t reserved2[3];
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/* 532-535 536-539 540-543 */
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#endif
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/* ========================================================== */
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};
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/*
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*******************************************************************************
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** ARECA SCSI sense data
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*******************************************************************************
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*/
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struct SENSE_DATA
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{
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uint8_t ErrorCode:7;
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#define SCSI_SENSE_CURRENT_ERRORS 0x70
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#define SCSI_SENSE_DEFERRED_ERRORS 0x71
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uint8_t Valid:1;
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uint8_t SegmentNumber;
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uint8_t SenseKey:4;
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uint8_t Reserved:1;
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uint8_t IncorrectLength:1;
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uint8_t EndOfMedia:1;
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uint8_t FileMark:1;
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uint8_t Information[4];
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uint8_t AdditionalSenseLength;
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uint8_t CommandSpecificInformation[4];
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uint8_t AdditionalSenseCode;
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uint8_t AdditionalSenseCodeQualifier;
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uint8_t FieldReplaceableUnitCode;
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uint8_t SenseKeySpecific[3];
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};
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/*
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*******************************************************************************
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** Outbound Interrupt Status Register - OISR
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*******************************************************************************
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*/
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#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
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#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
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#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
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#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
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#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
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#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
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#define ARCMSR_MU_OUTBOUND_HANDLE_INT \
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(ARCMSR_MU_OUTBOUND_MESSAGE0_INT \
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|ARCMSR_MU_OUTBOUND_MESSAGE1_INT \
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|ARCMSR_MU_OUTBOUND_DOORBELL_INT \
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|ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \
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|ARCMSR_MU_OUTBOUND_PCI_INT)
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/*
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*******************************************************************************
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** Outbound Interrupt Mask Register - OIMR
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*******************************************************************************
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*/
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#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
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#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
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#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
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#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
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#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
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#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
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#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
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extern void arcmsr_post_Qbuffer(struct AdapterControlBlock *acb);
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extern struct class_device_attribute *arcmsr_host_attrs[];
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extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *acb);
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void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);
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