Stephen Boyd 36d68f64c4 ARM: Add Krait L2 register accessor functions ... Krait CPUs have a handful of L2 cache controller registers that live behind a cp15 based indirection register. First you program the indirection register (l2cpselr) to point the L2 'window' register (l2cpdr) at what you want to read/write. Then you read/write the 'window' register to do what you want. The l2cpselr register is not banked per-cpu so we must lock around accesses to it to prevent other CPUs from re-pointing l2cpdr underneath us. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2018-10-17 13:14:33 -07:00
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bL_switcher_dummy_if.c	ARM: 8743/1: bL_switcher: add MODULE_LICENSE tag	2018-01-21 15:32:27 +00:00
bL_switcher.c
dmabounce.c
firmware.c
it8152.c
Kconfig	ARM: Add Krait L2 register accessor functions	2018-10-17 13:14:33 -07:00
krait-l2-accessors.c	ARM: Add Krait L2 register accessor functions	2018-10-17 13:14:33 -07:00
locomo.c	PM: ARM: locomo: Drop suspend and resume bus type callbacks	2017-10-05 00:40:57 +02:00
Makefile	ARM: Add Krait L2 register accessor functions	2018-10-17 13:14:33 -07:00
mcpm_entry.c	ARM: mcpm, perf/arm-cci: export mcpm_is_available	2018-05-29 16:53:16 +01:00
mcpm_head.S
mcpm_platsmp.c
sa1111.c	ARM: sa1111: map interrupt numbers through irqdomain	2017-11-29 10:57:41 +00:00
scoop.c
secure_cntvoff.S	ARM: smp: Add initialization of CNTVOFF	2018-05-08 14:50:42 +02:00
sharpsl_param.c
vlock.h
vlock.S