forked from luck/tmp_suning_uos_patched
98f4222150
Based on CPU type choose generic omap3 or omap3430 specific cpuidle parameters. Parameters for omap3430 were measured on Nokia N900 device and added by commit5a1b1d3a9e("OMAP3: RX-51: Pass cpu idle parameters") which were later removed by commit231900afba("ARM: OMAP3: cpuidle - remove rx51 cpuidle parameters table") due to huge code complexity. This patch brings cpuidle parameters for omap3430 devices again, but uses simple condition based on CPU type. Fixes:231900afba("ARM: OMAP3: cpuidle - remove rx51 cpuidle parameters table") Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
405 lines
10 KiB
C
405 lines
10 KiB
C
/*
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* linux/arch/arm/mach-omap2/cpuidle34xx.c
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*
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* OMAP3 CPU IDLE Routines
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*
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* Copyright (C) 2008 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Karthik Dasu <karthik-dp@ti.com>
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*
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* Copyright (C) 2006 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Based on pm.c for omap2
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/sched.h>
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#include <linux/cpuidle.h>
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#include <linux/export.h>
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#include <linux/cpu_pm.h>
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#include <asm/cpuidle.h>
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#include "powerdomain.h"
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#include "clockdomain.h"
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#include "pm.h"
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#include "control.h"
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#include "common.h"
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#include "soc.h"
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/* Mach specific information to be recorded in the C-state driver_data */
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struct omap3_idle_statedata {
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u8 mpu_state;
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u8 core_state;
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u8 per_min_state;
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u8 flags;
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};
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static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
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/*
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* Possible flag bits for struct omap3_idle_statedata.flags:
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*
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* OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
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* inactive. This in turn prevents the MPU DPLL from entering autoidle
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* mode, so wakeup latency is greatly reduced, at the cost of additional
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* energy consumption. This also prevents the CORE clockdomain from
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* entering idle.
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*/
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#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE BIT(0)
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/*
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* Prevent PER OFF if CORE is not in RETention or OFF as this would
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* disable PER wakeups completely.
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*/
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static struct omap3_idle_statedata omap3_idle_data[] = {
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{
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.mpu_state = PWRDM_POWER_ON,
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.core_state = PWRDM_POWER_ON,
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/* In C1 do not allow PER state lower than CORE state */
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.per_min_state = PWRDM_POWER_ON,
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.flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
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},
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{
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.mpu_state = PWRDM_POWER_ON,
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.core_state = PWRDM_POWER_ON,
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.per_min_state = PWRDM_POWER_RET,
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},
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{
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.mpu_state = PWRDM_POWER_RET,
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.core_state = PWRDM_POWER_ON,
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.per_min_state = PWRDM_POWER_RET,
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},
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{
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.mpu_state = PWRDM_POWER_OFF,
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.core_state = PWRDM_POWER_ON,
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.per_min_state = PWRDM_POWER_RET,
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},
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{
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.mpu_state = PWRDM_POWER_RET,
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.core_state = PWRDM_POWER_RET,
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.per_min_state = PWRDM_POWER_OFF,
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},
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{
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.mpu_state = PWRDM_POWER_OFF,
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.core_state = PWRDM_POWER_RET,
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.per_min_state = PWRDM_POWER_OFF,
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},
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{
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.mpu_state = PWRDM_POWER_OFF,
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.core_state = PWRDM_POWER_OFF,
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.per_min_state = PWRDM_POWER_OFF,
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},
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};
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/**
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* omap3_enter_idle - Programs OMAP3 to enter the specified state
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* @dev: cpuidle device
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* @drv: cpuidle driver
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* @index: the index of state to be entered
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*/
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static int omap3_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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struct omap3_idle_statedata *cx = &omap3_idle_data[index];
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if (omap_irq_pending() || need_resched())
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goto return_sleep_time;
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/* Deny idle for C1 */
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if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
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clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
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} else {
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pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
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pwrdm_set_next_pwrst(core_pd, cx->core_state);
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}
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/*
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* Call idle CPU PM enter notifier chain so that
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* VFP context is saved.
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*/
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if (cx->mpu_state == PWRDM_POWER_OFF)
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cpu_pm_enter();
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/* Execute ARM wfi */
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omap_sram_idle();
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/*
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* Call idle CPU PM enter notifier chain to restore
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* VFP context.
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*/
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if (cx->mpu_state == PWRDM_POWER_OFF &&
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pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
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cpu_pm_exit();
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/* Re-allow idle for C1 */
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if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
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clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
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return_sleep_time:
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return index;
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}
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/**
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* next_valid_state - Find next valid C-state
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* @dev: cpuidle device
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* @drv: cpuidle driver
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* @index: Index of currently selected c-state
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*
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* If the state corresponding to index is valid, index is returned back
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* to the caller. Else, this function searches for a lower c-state which is
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* still valid (as defined in omap3_power_states[]) and returns its index.
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*
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* A state is valid if the 'valid' field is enabled and
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* if it satisfies the enable_off_mode condition.
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*/
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static int next_valid_state(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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struct omap3_idle_statedata *cx = &omap3_idle_data[index];
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u32 mpu_deepest_state = PWRDM_POWER_RET;
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u32 core_deepest_state = PWRDM_POWER_RET;
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int idx;
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int next_index = 0; /* C1 is the default value */
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if (enable_off_mode) {
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mpu_deepest_state = PWRDM_POWER_OFF;
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/*
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* Erratum i583: valable for ES rev < Es1.2 on 3630.
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* CORE OFF mode is not supported in a stable form, restrict
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* instead the CORE state to RET.
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*/
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if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
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core_deepest_state = PWRDM_POWER_OFF;
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}
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/* Check if current state is valid */
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if ((cx->mpu_state >= mpu_deepest_state) &&
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(cx->core_state >= core_deepest_state))
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return index;
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/*
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* Drop to next valid state.
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* Start search from the next (lower) state.
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*/
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for (idx = index - 1; idx >= 0; idx--) {
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cx = &omap3_idle_data[idx];
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if ((cx->mpu_state >= mpu_deepest_state) &&
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(cx->core_state >= core_deepest_state)) {
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next_index = idx;
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break;
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}
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}
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return next_index;
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}
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/**
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* omap3_enter_idle_bm - Checks for any bus activity
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* @dev: cpuidle device
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* @drv: cpuidle driver
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* @index: array index of target state to be programmed
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*
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* This function checks for any pending activity and then programs
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* the device to the specified or a safer state.
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*/
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static int omap3_enter_idle_bm(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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int new_state_idx, ret;
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u8 per_next_state, per_saved_state;
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struct omap3_idle_statedata *cx;
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/*
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* Use only C1 if CAM is active.
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* CAM does not have wakeup capability in OMAP3.
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*/
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if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
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new_state_idx = drv->safe_state_index;
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else
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new_state_idx = next_valid_state(dev, drv, index);
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/*
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* FIXME: we currently manage device-specific idle states
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* for PER and CORE in combination with CPU-specific
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* idle states. This is wrong, and device-specific
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* idle management needs to be separated out into
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* its own code.
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*/
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/* Program PER state */
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cx = &omap3_idle_data[new_state_idx];
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per_next_state = pwrdm_read_next_pwrst(per_pd);
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per_saved_state = per_next_state;
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if (per_next_state < cx->per_min_state) {
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per_next_state = cx->per_min_state;
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pwrdm_set_next_pwrst(per_pd, per_next_state);
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}
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ret = omap3_enter_idle(dev, drv, new_state_idx);
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/* Restore original PER state if it was modified */
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if (per_next_state != per_saved_state)
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pwrdm_set_next_pwrst(per_pd, per_saved_state);
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return ret;
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}
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static struct cpuidle_driver omap3_idle_driver = {
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.name = "omap3_idle",
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.owner = THIS_MODULE,
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.states = {
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 2 + 2,
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.target_residency = 5,
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.name = "C1",
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.desc = "MPU ON + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 10 + 10,
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.target_residency = 30,
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.name = "C2",
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.desc = "MPU ON + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 50 + 50,
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.target_residency = 300,
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.name = "C3",
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.desc = "MPU RET + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 1500 + 1800,
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.target_residency = 4000,
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.name = "C4",
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.desc = "MPU OFF + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 2500 + 7500,
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.target_residency = 12000,
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.name = "C5",
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.desc = "MPU RET + CORE RET",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 3000 + 8500,
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.target_residency = 15000,
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.name = "C6",
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.desc = "MPU OFF + CORE RET",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 10000 + 30000,
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.target_residency = 30000,
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.name = "C7",
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.desc = "MPU OFF + CORE OFF",
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},
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},
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.state_count = ARRAY_SIZE(omap3_idle_data),
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.safe_state_index = 0,
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};
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/*
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* Numbers based on measurements made in October 2009 for PM optimized kernel
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* with CPU freq enabled on device Nokia N900. Assumes OPP2 (main idle OPP,
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* and worst case latencies).
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*/
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static struct cpuidle_driver omap3430_idle_driver = {
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.name = "omap3430_idle",
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.owner = THIS_MODULE,
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.states = {
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 110 + 162,
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.target_residency = 5,
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.name = "C1",
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.desc = "MPU ON + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 106 + 180,
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.target_residency = 309,
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.name = "C2",
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.desc = "MPU ON + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 107 + 410,
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.target_residency = 46057,
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.name = "C3",
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.desc = "MPU RET + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 121 + 3374,
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.target_residency = 46057,
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.name = "C4",
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.desc = "MPU OFF + CORE ON",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 855 + 1146,
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.target_residency = 46057,
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.name = "C5",
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.desc = "MPU RET + CORE RET",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 7580 + 4134,
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.target_residency = 484329,
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.name = "C6",
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.desc = "MPU OFF + CORE RET",
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},
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{
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.enter = omap3_enter_idle_bm,
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.exit_latency = 7505 + 15274,
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.target_residency = 484329,
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.name = "C7",
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.desc = "MPU OFF + CORE OFF",
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},
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},
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.state_count = ARRAY_SIZE(omap3_idle_data),
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.safe_state_index = 0,
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};
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/* Public functions */
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/**
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* omap3_idle_init - Init routine for OMAP3 idle
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*
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* Registers the OMAP3 specific cpuidle driver to the cpuidle
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* framework with the valid set of states.
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*/
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int __init omap3_idle_init(void)
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{
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mpu_pd = pwrdm_lookup("mpu_pwrdm");
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core_pd = pwrdm_lookup("core_pwrdm");
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per_pd = pwrdm_lookup("per_pwrdm");
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cam_pd = pwrdm_lookup("cam_pwrdm");
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if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
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return -ENODEV;
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if (cpu_is_omap3430())
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return cpuidle_register(&omap3430_idle_driver, NULL);
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else
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return cpuidle_register(&omap3_idle_driver, NULL);
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}
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