forked from luck/tmp_suning_uos_patched
8644cdf972
The omap3isp MMIO register block is contiguous in the MMIO register space apart from the fact that the ISP IOMMU register block is in the middle of the area. Ioremap it at two occasions, and keep the rest of the layout of the register space internal to the omap3isp driver. Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
70 lines
2.3 KiB
C
70 lines
2.3 KiB
C
/*
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* This file contains the processor specific definitions of the TI OMAP34XX.
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*
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* Copyright (C) 2007 Texas Instruments.
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* Copyright (C) 2007 Nokia Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_OMAP3_H
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#define __ASM_ARCH_OMAP3_H
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/*
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* Please place only base defines here and put the rest in device
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* specific headers.
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*/
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#define L4_34XX_BASE 0x48000000
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#define L4_WK_34XX_BASE 0x48300000
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#define L4_PER_34XX_BASE 0x49000000
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#define L4_EMU_34XX_BASE 0x54000000
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#define L3_34XX_BASE 0x68000000
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#define L4_WK_AM33XX_BASE 0x44C00000
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#define OMAP3430_32KSYNCT_BASE 0x48320000
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#define OMAP3430_CM_BASE 0x48004800
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#define OMAP3430_PRM_BASE 0x48306800
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#define OMAP343X_SMS_BASE 0x6C000000
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#define OMAP343X_SDRC_BASE 0x6D000000
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#define OMAP34XX_GPMC_BASE 0x6E000000
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#define OMAP343X_SCM_BASE 0x48002000
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#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
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#define OMAP34XX_IC_BASE 0x48200000
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#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
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#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
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#define OMAP3430_ISP_BASE2 (OMAP3430_ISP_BASE + 0x1800)
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#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
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#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
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#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
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#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
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#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
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#define OMAP34XX_SR1_BASE 0x480C9000
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#define OMAP34XX_SR2_BASE 0x480CB000
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#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
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/* Security */
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#define OMAP34XX_SEC_BASE (L4_34XX_BASE + 0xA0000)
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#define OMAP34XX_SEC_SHA1MD5_BASE (OMAP34XX_SEC_BASE + 0x23000)
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#define OMAP34XX_SEC_AES_BASE (OMAP34XX_SEC_BASE + 0x25000)
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#endif /* __ASM_ARCH_OMAP3_H */
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