forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
378 lines
11 KiB
C
378 lines
11 KiB
C
/* cyberstorm.c: Driver for CyberStorm SCSI Controller.
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*
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* Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
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*
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* The CyberStorm SCSI driver is based on David S. Miller's ESP driver
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* for the Sparc computers.
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*
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* This work was made possible by Phase5 who willingly (and most generously)
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* supported me with hardware and all the information I needed.
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*/
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/* TODO:
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*
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* 1) Figure out how to make a cleaner merge with the sparc driver with regard
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* to the caches and the Sparc MMU mapping.
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* 2) Make as few routines required outside the generic driver. A lot of the
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* routines in this file used to be inline!
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/blkdev.h>
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#include <linux/proc_fs.h>
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#include <linux/stat.h>
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#include <linux/interrupt.h>
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#include "scsi.h"
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#include <scsi/scsi_host.h>
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#include "NCR53C9x.h"
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#include <linux/zorro.h>
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#include <asm/irq.h>
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#include <asm/amigaints.h>
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#include <asm/amigahw.h>
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#include <asm/pgtable.h>
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/* The controller registers can be found in the Z2 config area at these
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* offsets:
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*/
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#define CYBER_ESP_ADDR 0xf400
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#define CYBER_DMA_ADDR 0xf800
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/* The CyberStorm DMA interface */
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struct cyber_dma_registers {
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volatile unsigned char dma_addr0; /* DMA address (MSB) [0x000] */
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unsigned char dmapad1[1];
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volatile unsigned char dma_addr1; /* DMA address [0x002] */
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unsigned char dmapad2[1];
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volatile unsigned char dma_addr2; /* DMA address [0x004] */
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unsigned char dmapad3[1];
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volatile unsigned char dma_addr3; /* DMA address (LSB) [0x006] */
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unsigned char dmapad4[0x3fb];
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volatile unsigned char cond_reg; /* DMA cond (ro) [0x402] */
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#define ctrl_reg cond_reg /* DMA control (wo) [0x402] */
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};
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/* DMA control bits */
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#define CYBER_DMA_LED 0x80 /* HD led control 1 = on */
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#define CYBER_DMA_WRITE 0x40 /* DMA direction. 1 = write */
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#define CYBER_DMA_Z3 0x20 /* 16 (Z2) or 32 (CHIP/Z3) bit DMA transfer */
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/* DMA status bits */
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#define CYBER_DMA_HNDL_INTR 0x80 /* DMA IRQ pending? */
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/* The bits below appears to be Phase5 Debug bits only; they were not
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* described by Phase5 so using them may seem a bit stupid...
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*/
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#define CYBER_HOST_ID 0x02 /* If set, host ID should be 7, otherwise
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* it should be 6.
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*/
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#define CYBER_SLOW_CABLE 0x08 /* If *not* set, assume SLOW_CABLE */
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static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
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static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
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static void dma_dump_state(struct NCR_ESP *esp);
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static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
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static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
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static void dma_ints_off(struct NCR_ESP *esp);
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static void dma_ints_on(struct NCR_ESP *esp);
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static int dma_irq_p(struct NCR_ESP *esp);
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static void dma_led_off(struct NCR_ESP *esp);
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static void dma_led_on(struct NCR_ESP *esp);
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static int dma_ports_p(struct NCR_ESP *esp);
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static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
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static unsigned char ctrl_data = 0; /* Keep backup of the stuff written
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* to ctrl_reg. Always write a copy
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* to this register when writing to
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* the hardware register!
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*/
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static volatile unsigned char cmd_buffer[16];
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/* This is where all commands are put
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* before they are transferred to the ESP chip
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* via PIO.
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*/
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/***************************************************************** Detection */
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int __init cyber_esp_detect(Scsi_Host_Template *tpnt)
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{
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struct NCR_ESP *esp;
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struct zorro_dev *z = NULL;
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unsigned long address;
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while ((z = zorro_find_device(ZORRO_WILDCARD, z))) {
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unsigned long board = z->resource.start;
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if ((z->id == ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM ||
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z->id == ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060) &&
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request_mem_region(board+CYBER_ESP_ADDR,
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sizeof(struct ESP_regs), "NCR53C9x")) {
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/* Figure out if this is a CyberStorm or really a
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* Fastlane/Blizzard Mk II by looking at the board size.
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* CyberStorm maps 64kB
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* (ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM does anyway)
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*/
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if(z->resource.end-board != 0xffff) {
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release_mem_region(board+CYBER_ESP_ADDR,
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sizeof(struct ESP_regs));
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return 0;
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}
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esp = esp_allocate(tpnt, (void *)board+CYBER_ESP_ADDR);
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/* Do command transfer with programmed I/O */
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esp->do_pio_cmds = 1;
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/* Required functions */
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esp->dma_bytes_sent = &dma_bytes_sent;
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esp->dma_can_transfer = &dma_can_transfer;
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esp->dma_dump_state = &dma_dump_state;
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esp->dma_init_read = &dma_init_read;
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esp->dma_init_write = &dma_init_write;
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esp->dma_ints_off = &dma_ints_off;
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esp->dma_ints_on = &dma_ints_on;
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esp->dma_irq_p = &dma_irq_p;
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esp->dma_ports_p = &dma_ports_p;
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esp->dma_setup = &dma_setup;
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/* Optional functions */
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esp->dma_barrier = 0;
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esp->dma_drain = 0;
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esp->dma_invalidate = 0;
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esp->dma_irq_entry = 0;
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esp->dma_irq_exit = 0;
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esp->dma_led_on = &dma_led_on;
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esp->dma_led_off = &dma_led_off;
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esp->dma_poll = 0;
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esp->dma_reset = 0;
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/* SCSI chip speed */
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esp->cfreq = 40000000;
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/* The DMA registers on the CyberStorm are mapped
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* relative to the device (i.e. in the same Zorro
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* I/O block).
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*/
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address = (unsigned long)ZTWO_VADDR(board);
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esp->dregs = (void *)(address + CYBER_DMA_ADDR);
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/* ESP register base */
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esp->eregs = (struct ESP_regs *)(address + CYBER_ESP_ADDR);
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/* Set the command buffer */
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esp->esp_command = cmd_buffer;
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esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);
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esp->irq = IRQ_AMIGA_PORTS;
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request_irq(IRQ_AMIGA_PORTS, esp_intr, SA_SHIRQ,
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"CyberStorm SCSI", esp->ehost);
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/* Figure out our scsi ID on the bus */
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/* The DMA cond flag contains a hardcoded jumper bit
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* which can be used to select host number 6 or 7.
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* However, even though it may change, we use a hardcoded
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* value of 7.
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*/
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esp->scsi_id = 7;
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/* We don't have a differential SCSI-bus. */
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esp->diff = 0;
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esp_initialize(esp);
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printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
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esps_running = esps_in_use;
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return esps_in_use;
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}
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}
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return 0;
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}
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/************************************************************* DMA Functions */
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static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
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{
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/* Since the CyberStorm DMA is fully dedicated to the ESP chip,
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* the number of bytes sent (to the ESP chip) equals the number
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* of bytes in the FIFO - there is no buffering in the DMA controller.
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* XXXX Do I read this right? It is from host to ESP, right?
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*/
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return fifo_count;
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}
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static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
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{
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/* I don't think there's any limit on the CyberDMA. So we use what
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* the ESP chip can handle (24 bit).
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*/
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unsigned long sz = sp->SCp.this_residual;
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if(sz > 0x1000000)
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sz = 0x1000000;
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return sz;
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}
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static void dma_dump_state(struct NCR_ESP *esp)
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{
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ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
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esp->esp_id, ((struct cyber_dma_registers *)
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(esp->dregs))->cond_reg));
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ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
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custom.intreqr, custom.intenar));
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}
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static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
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{
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struct cyber_dma_registers *dregs =
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(struct cyber_dma_registers *) esp->dregs;
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cache_clear(addr, length);
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addr &= ~(1);
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dregs->dma_addr0 = (addr >> 24) & 0xff;
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dregs->dma_addr1 = (addr >> 16) & 0xff;
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dregs->dma_addr2 = (addr >> 8) & 0xff;
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dregs->dma_addr3 = (addr ) & 0xff;
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ctrl_data &= ~(CYBER_DMA_WRITE);
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/* Check if physical address is outside Z2 space and of
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* block length/block aligned in memory. If this is the
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* case, enable 32 bit transfer. In all other cases, fall back
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* to 16 bit transfer.
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* Obviously 32 bit transfer should be enabled if the DMA address
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* and length are 32 bit aligned. However, this leads to some
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* strange behavior. Even 64 bit aligned addr/length fails.
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* Until I've found a reason for this, 32 bit transfer is only
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* used for full-block transfers (1kB).
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* -jskov
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*/
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#if 0
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if((addr & 0x3fc) || length & 0x3ff || ((addr > 0x200000) &&
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(addr < 0xff0000)))
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ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
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else
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ctrl_data |= CYBER_DMA_Z3; /* CHIP/Z3, do 32 bit DMA */
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#else
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ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
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#endif
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dregs->ctrl_reg = ctrl_data;
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}
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static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
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{
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struct cyber_dma_registers *dregs =
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(struct cyber_dma_registers *) esp->dregs;
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cache_push(addr, length);
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addr |= 1;
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dregs->dma_addr0 = (addr >> 24) & 0xff;
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dregs->dma_addr1 = (addr >> 16) & 0xff;
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dregs->dma_addr2 = (addr >> 8) & 0xff;
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dregs->dma_addr3 = (addr ) & 0xff;
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ctrl_data |= CYBER_DMA_WRITE;
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/* See comment above */
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#if 0
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if((addr & 0x3fc) || length & 0x3ff || ((addr > 0x200000) &&
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(addr < 0xff0000)))
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ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
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else
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ctrl_data |= CYBER_DMA_Z3; /* CHIP/Z3, do 32 bit DMA */
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#else
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ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */
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#endif
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dregs->ctrl_reg = ctrl_data;
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}
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static void dma_ints_off(struct NCR_ESP *esp)
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{
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disable_irq(esp->irq);
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}
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static void dma_ints_on(struct NCR_ESP *esp)
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{
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enable_irq(esp->irq);
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}
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static int dma_irq_p(struct NCR_ESP *esp)
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{
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/* It's important to check the DMA IRQ bit in the correct way! */
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return ((esp_read(esp->eregs->esp_status) & ESP_STAT_INTR) &&
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((((struct cyber_dma_registers *)(esp->dregs))->cond_reg) &
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CYBER_DMA_HNDL_INTR));
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}
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static void dma_led_off(struct NCR_ESP *esp)
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{
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ctrl_data &= ~CYBER_DMA_LED;
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((struct cyber_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
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}
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static void dma_led_on(struct NCR_ESP *esp)
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{
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ctrl_data |= CYBER_DMA_LED;
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((struct cyber_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
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}
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static int dma_ports_p(struct NCR_ESP *esp)
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{
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return ((custom.intenar) & IF_PORTS);
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}
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static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
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{
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/* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
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* so when (write) is true, it actually means READ!
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*/
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if(write){
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dma_init_read(esp, addr, count);
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} else {
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dma_init_write(esp, addr, count);
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}
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}
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#define HOSTS_C
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int cyber_esp_release(struct Scsi_Host *instance)
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{
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#ifdef MODULE
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unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
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esp_deallocate((struct NCR_ESP *)instance->hostdata);
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esp_release();
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release_mem_region(address, sizeof(struct ESP_regs));
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free_irq(IRQ_AMIGA_PORTS, esp_intr);
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#endif
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return 1;
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}
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static Scsi_Host_Template driver_template = {
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.proc_name = "esp-cyberstorm",
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.proc_info = esp_proc_info,
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.name = "CyberStorm SCSI",
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.detect = cyber_esp_detect,
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.slave_alloc = esp_slave_alloc,
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.slave_destroy = esp_slave_destroy,
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.release = cyber_esp_release,
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.queuecommand = esp_queue,
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.eh_abort_handler = esp_abort,
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.eh_bus_reset_handler = esp_reset,
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.can_queue = 7,
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.this_id = 7,
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.sg_tablesize = SG_ALL,
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.cmd_per_lun = 1,
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.use_clustering = ENABLE_CLUSTERING
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};
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#include "scsi_module.c"
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MODULE_LICENSE("GPL");
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