forked from luck/tmp_suning_uos_patched
8593fbc68b
Hopefully the last iteration on this! The handling of out of band data on NAND was accompanied by tons of fruitless discussions and halfarsed patches to make it work for a particular problem. Sufficiently annoyed by I all those "I know it better" mails and the resonable amount of discarded "it solves my problem" patches, I finally decided to go for the big rework. After removing the _ecc variants of mtd read/write functions the solution to satisfy the various requirements was to refactor the read/write _oob functions in mtd. The major change is that read/write_oob now takes a pointer to an operation descriptor structure "struct mtd_oob_ops".instead of having a function with at least seven arguments. read/write_oob which should probably renamed to a more descriptive name, can do the following tasks: - read/write out of band data - read/write data content and out of band data - read/write raw data content and out of band data (ecc disabled) struct mtd_oob_ops has a mode field, which determines the oob handling mode. Aside of the MTD_OOB_RAW mode, which is intended to be especially for diagnostic purposes and some internal functions e.g. bad block table creation, the other two modes are for mtd clients: MTD_OOB_PLACE puts/gets the given oob data exactly to/from the place which is described by the ooboffs and ooblen fields of the mtd_oob_ops strcuture. It's up to the caller to make sure that the byte positions are not used by the ECC placement algorithms. MTD_OOB_AUTO puts/gets the given oob data automaticaly to/from the places in the out of band area which are described by the oobfree tuples in the ecclayout data structre which is associated to the devicee. The decision whether data plus oob or oob only handling is done depends on the setting of the datbuf member of the data structure. When datbuf == NULL then the internal read/write_oob functions are selected, otherwise the read/write data routines are invoked. Tested on a few platforms with all variants. Please be aware of possible regressions for your particular device / application scenario Disclaimer: Any whining will be ignored from those who just contributed "hot air blurb" and never sat down to tackle the underlying problem of the mess in the NAND driver grown over time and the big chunk of work to fix up the existing users. The problem was not the holiness of the existing MTD interfaces. The problems was the lack of time to go for the big overhaul. It's easy to add more mess to the existing one, but it takes alot of effort to go for a real solution. Improvements and bugfixes are welcome! Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
561 lines
19 KiB
C
561 lines
19 KiB
C
/*
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* linux/include/linux/mtd/nand.h
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*
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* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
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* Steven J. Hill <sjhill@realitydiluted.com>
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* Thomas Gleixner <tglx@linutronix.de>
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*
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* $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Info:
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* Contains standard defines and IDs for NAND flash devices
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*
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* Changelog:
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* See git changelog.
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*/
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#ifndef __LINUX_MTD_NAND_H
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#define __LINUX_MTD_NAND_H
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#include <linux/config.h>
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#include <linux/wait.h>
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#include <linux/spinlock.h>
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#include <linux/mtd/mtd.h>
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struct mtd_info;
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/* Scan and identify a NAND device */
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extern int nand_scan (struct mtd_info *mtd, int max_chips);
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/* Free resources held by the NAND device */
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extern void nand_release (struct mtd_info *mtd);
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/* The maximum number of NAND chips in an array */
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#define NAND_MAX_CHIPS 8
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/* This constant declares the max. oobsize / page, which
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* is supported now. If you add a chip with bigger oobsize/page
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* adjust this accordingly.
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*/
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#define NAND_MAX_OOBSIZE 64
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#define NAND_MAX_PAGESIZE 2048
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/*
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* Constants for hardware specific CLE/ALE/NCE function
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*
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* These are bits which can be or'ed to set/clear multiple
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* bits in one go.
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*/
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/* Select the chip by setting nCE to low */
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#define NAND_NCE 0x01
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/* Select the command latch by setting CLE to high */
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#define NAND_CLE 0x02
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/* Select the address latch by setting ALE to high */
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#define NAND_ALE 0x04
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#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
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#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
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#define NAND_CTRL_CHANGE 0x80
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/*
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* Standard NAND flash commands
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*/
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#define NAND_CMD_READ0 0
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#define NAND_CMD_READ1 1
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#define NAND_CMD_PAGEPROG 0x10
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#define NAND_CMD_READOOB 0x50
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#define NAND_CMD_ERASE1 0x60
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_SEQIN 0x80
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#define NAND_CMD_READID 0x90
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#define NAND_CMD_ERASE2 0xd0
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#define NAND_CMD_RESET 0xff
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/* Extended commands for large page devices */
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#define NAND_CMD_READSTART 0x30
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#define NAND_CMD_CACHEDPROG 0x15
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/* Extended commands for AG-AND device */
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/*
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* Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
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* there is no way to distinguish that from NAND_CMD_READ0
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* until the remaining sequence of commands has been completed
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* so add a high order bit and mask it off in the command.
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*/
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#define NAND_CMD_DEPLETE1 0x100
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#define NAND_CMD_DEPLETE2 0x38
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_STATUS_ERROR 0x72
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/* multi-bank error status (banks 0-3) */
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#define NAND_CMD_STATUS_ERROR0 0x73
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#define NAND_CMD_STATUS_ERROR1 0x74
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#define NAND_CMD_STATUS_ERROR2 0x75
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#define NAND_CMD_STATUS_ERROR3 0x76
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#define NAND_CMD_STATUS_RESET 0x7f
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#define NAND_CMD_STATUS_CLEAR 0xff
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#define NAND_CMD_NONE -1
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/* Status bits */
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#define NAND_STATUS_FAIL 0x01
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#define NAND_STATUS_FAIL_N1 0x02
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#define NAND_STATUS_TRUE_READY 0x20
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#define NAND_STATUS_READY 0x40
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#define NAND_STATUS_WP 0x80
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/*
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* Constants for ECC_MODES
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*/
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typedef enum {
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NAND_ECC_NONE,
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NAND_ECC_SOFT,
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NAND_ECC_HW,
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NAND_ECC_HW_SYNDROME,
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} nand_ecc_modes_t;
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/*
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* Constants for Hardware ECC
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*/
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/* Reset Hardware ECC for read */
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#define NAND_ECC_READ 0
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/* Reset Hardware ECC for write */
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#define NAND_ECC_WRITE 1
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/* Enable Hardware ECC before syndrom is read back from flash */
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#define NAND_ECC_READSYN 2
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/* Bit mask for flags passed to do_nand_read_ecc */
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#define NAND_GET_DEVICE 0x80
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/* Option constants for bizarre disfunctionality and real
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* features
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*/
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/* Chip can not auto increment pages */
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#define NAND_NO_AUTOINCR 0x00000001
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/* Buswitdh is 16 bit */
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#define NAND_BUSWIDTH_16 0x00000002
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/* Device supports partial programming without padding */
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#define NAND_NO_PADDING 0x00000004
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/* Chip has cache program function */
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#define NAND_CACHEPRG 0x00000008
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/* Chip has copy back function */
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#define NAND_COPYBACK 0x00000010
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/* AND Chip which has 4 banks and a confusing page / block
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* assignment. See Renesas datasheet for further information */
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#define NAND_IS_AND 0x00000020
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/* Chip has a array of 4 pages which can be read without
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* additional ready /busy waits */
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#define NAND_4PAGE_ARRAY 0x00000040
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/* Chip requires that BBT is periodically rewritten to prevent
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* bits from adjacent blocks from 'leaking' in altering data.
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* This happens with the Renesas AG-AND chips, possibly others. */
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#define BBT_AUTO_REFRESH 0x00000080
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/* Chip does not require ready check on read. True
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* for all large page devices, as they do not support
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* autoincrement.*/
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#define NAND_NO_READRDY 0x00000100
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/* Options valid for Samsung large page devices */
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#define NAND_SAMSUNG_LP_OPTIONS \
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(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
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/* Macros to identify the above */
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#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
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#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
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#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
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#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
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/* Mask to zero out the chip options, which come from the id table */
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#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
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/* Non chip related options */
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/* Use a flash based bad block table. This option is passed to the
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* default bad block table function. */
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#define NAND_USE_FLASH_BBT 0x00010000
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/* This option skips the bbt scan during initialization. */
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#define NAND_SKIP_BBTSCAN 0x00020000
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/* Options set by nand scan */
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/* Nand scan has allocated controller struct */
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#define NAND_CONTROLLER_ALLOC 0x80000000
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/*
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* nand_state_t - chip states
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* Enumeration for NAND flash chip state
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*/
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typedef enum {
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FL_READY,
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FL_READING,
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FL_WRITING,
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FL_ERASING,
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FL_SYNCING,
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FL_CACHEDPRG,
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FL_PM_SUSPENDED,
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} nand_state_t;
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/* Keep gcc happy */
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struct nand_chip;
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/**
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* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
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* @lock: protection lock
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* @active: the mtd device which holds the controller currently
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* @wq: wait queue to sleep on if a NAND operation is in progress
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* used instead of the per chip wait queue when a hw controller is available
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*/
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struct nand_hw_control {
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spinlock_t lock;
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struct nand_chip *active;
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wait_queue_head_t wq;
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};
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/**
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* struct nand_ecc_ctrl - Control structure for ecc
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* @mode: ecc mode
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* @steps: number of ecc steps per page
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* @size: data bytes per ecc step
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* @bytes: ecc bytes per step
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* @total: total number of ecc bytes per page
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* @prepad: padding information for syndrome based ecc generators
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* @postpad: padding information for syndrome based ecc generators
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* @hwctl: function to control hardware ecc generator. Must only
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* be provided if an hardware ECC is available
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* @calculate: function for ecc calculation or readback from ecc hardware
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* @correct: function for ecc correction, matching to ecc generator (sw/hw)
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* @read_page: function to read a page according to the ecc generator requirements
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* @write_page: function to write a page according to the ecc generator requirements
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*/
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struct nand_ecc_ctrl {
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nand_ecc_modes_t mode;
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int steps;
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int size;
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int bytes;
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int total;
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int prepad;
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int postpad;
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struct nand_ecclayout *layout;
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void (*hwctl)(struct mtd_info *mtd, int mode);
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int (*calculate)(struct mtd_info *mtd,
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const uint8_t *dat,
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uint8_t *ecc_code);
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int (*correct)(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc,
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uint8_t *calc_ecc);
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int (*read_page)(struct mtd_info *mtd,
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struct nand_chip *chip,
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uint8_t *buf);
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void (*write_page)(struct mtd_info *mtd,
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struct nand_chip *chip,
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const uint8_t *buf);
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};
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/**
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* struct nand_buffers - buffer structure for read/write
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* @ecccalc: buffer for calculated ecc
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* @ecccode: buffer for ecc read from flash
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* @oobwbuf: buffer for write oob data
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* @databuf: buffer for data - dynamically sized
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* @oobrbuf: buffer to read oob data
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*
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* Do not change the order of buffers. databuf and oobrbuf must be in
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* consecutive order.
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*/
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struct nand_buffers {
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uint8_t ecccalc[NAND_MAX_OOBSIZE];
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uint8_t ecccode[NAND_MAX_OOBSIZE];
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uint8_t oobwbuf[NAND_MAX_OOBSIZE];
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uint8_t databuf[NAND_MAX_PAGESIZE];
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uint8_t oobrbuf[NAND_MAX_OOBSIZE];
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};
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/**
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* struct nand_chip - NAND Private Flash Chip Data
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* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
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* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
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* @read_byte: [REPLACEABLE] read one byte from the chip
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* @read_word: [REPLACEABLE] read one word from the chip
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* @write_buf: [REPLACEABLE] write data from the buffer to the chip
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* @read_buf: [REPLACEABLE] read data from the chip into the buffer
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* @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
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* @select_chip: [REPLACEABLE] select chip nr
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* @block_bad: [REPLACEABLE] check, if the block is bad
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* @block_markbad: [REPLACEABLE] mark the block bad
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* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
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* ALE/CLE/nCE. Also used to write command and address
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* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
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* If set to NULL no access to ready/busy is available and the ready/busy information
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* is read from the chip status register
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* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
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* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
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* @ecc: [BOARDSPECIFIC] ecc control ctructure
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* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
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* @scan_bbt: [REPLACEABLE] function to scan bad block table
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* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
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* @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
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* @state: [INTERN] the current state of the NAND device
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* @page_shift: [INTERN] number of address bits in a page (column address bits)
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* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
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* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
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* @chip_shift: [INTERN] number of address bits in one chip
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* @datbuf: [INTERN] internal buffer for one page + oob
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* @oobbuf: [INTERN] oob buffer for one eraseblock
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* @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
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* @data_poi: [INTERN] pointer to a data buffer
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* @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
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* special functionality. See the defines for further explanation
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* @badblockpos: [INTERN] position of the bad block marker in the oob area
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* @numchips: [INTERN] number of physical chips
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* @chipsize: [INTERN] the size of one chip for multichip arrays
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* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
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* @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
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* @ecclayout: [REPLACEABLE] the default ecc placement scheme
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* @bbt: [INTERN] bad block table pointer
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* @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
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* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
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* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
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* @controller: [REPLACEABLE] a pointer to a hardware controller structure
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* which is shared among multiple independend devices
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* @priv: [OPTIONAL] pointer to private chip date
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* @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
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* (determine if errors are correctable)
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*/
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struct nand_chip {
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void __iomem *IO_ADDR_R;
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void __iomem *IO_ADDR_W;
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uint8_t (*read_byte)(struct mtd_info *mtd);
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u16 (*read_word)(struct mtd_info *mtd);
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void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
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void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
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int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
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void (*select_chip)(struct mtd_info *mtd, int chip);
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int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
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int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
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void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
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unsigned int ctrl);
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int (*dev_ready)(struct mtd_info *mtd);
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void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
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int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
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void (*erase_cmd)(struct mtd_info *mtd, int page);
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int (*scan_bbt)(struct mtd_info *mtd);
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int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
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int chip_delay;
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unsigned int options;
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int page_shift;
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int phys_erase_shift;
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int bbt_erase_shift;
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int chip_shift;
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int numchips;
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unsigned long chipsize;
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int pagemask;
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int pagebuf;
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int badblockpos;
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nand_state_t state;
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uint8_t *oob_poi;
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struct nand_hw_control *controller;
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struct nand_ecclayout *ecclayout;
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struct nand_ecc_ctrl ecc;
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struct nand_buffers buffers;
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struct nand_hw_control hwcontrol;
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struct mtd_oob_ops ops;
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uint8_t *bbt;
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struct nand_bbt_descr *bbt_td;
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struct nand_bbt_descr *bbt_md;
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struct nand_bbt_descr *badblock_pattern;
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void *priv;
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};
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/*
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* NAND Flash Manufacturer ID Codes
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*/
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#define NAND_MFR_TOSHIBA 0x98
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#define NAND_MFR_SAMSUNG 0xec
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#define NAND_MFR_FUJITSU 0x04
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#define NAND_MFR_NATIONAL 0x8f
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#define NAND_MFR_RENESAS 0x07
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#define NAND_MFR_STMICRO 0x20
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#define NAND_MFR_HYNIX 0xad
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/**
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* struct nand_flash_dev - NAND Flash Device ID Structure
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*
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* @name: Identify the device type
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* @id: device ID code
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* @pagesize: Pagesize in bytes. Either 256 or 512 or 0
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* If the pagesize is 0, then the real pagesize
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* and the eraseize are determined from the
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* extended id bytes in the chip
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* @erasesize: Size of an erase block in the flash device.
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* @chipsize: Total chipsize in Mega Bytes
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* @options: Bitfield to store chip relevant options
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*/
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struct nand_flash_dev {
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char *name;
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int id;
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unsigned long pagesize;
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unsigned long chipsize;
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unsigned long erasesize;
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unsigned long options;
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};
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/**
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* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
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* @name: Manufacturer name
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* @id: manufacturer ID code of device.
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*/
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struct nand_manufacturers {
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int id;
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char * name;
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};
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extern struct nand_flash_dev nand_flash_ids[];
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extern struct nand_manufacturers nand_manuf_ids[];
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/**
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* struct nand_bbt_descr - bad block table descriptor
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* @options: options for this descriptor
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* @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
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* when bbt is searched, then we store the found bbts pages here.
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* Its an array and supports up to 8 chips now
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* @offs: offset of the pattern in the oob area of the page
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* @veroffs: offset of the bbt version counter in the oob are of the page
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* @version: version read from the bbt page during scan
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* @len: length of the pattern, if 0 no pattern check is performed
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* @maxblocks: maximum number of blocks to search for a bbt. This number of
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* blocks is reserved at the end of the device where the tables are
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* written.
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* @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
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* bad) block in the stored bbt
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* @pattern: pattern to identify bad block table or factory marked good /
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* bad blocks, can be NULL, if len = 0
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*
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* Descriptor for the bad block table marker and the descriptor for the
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* pattern which identifies good and bad blocks. The assumption is made
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* that the pattern and the version count are always located in the oob area
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* of the first block.
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*/
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struct nand_bbt_descr {
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int options;
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int pages[NAND_MAX_CHIPS];
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int offs;
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int veroffs;
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uint8_t version[NAND_MAX_CHIPS];
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int len;
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int maxblocks;
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int reserved_block_code;
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uint8_t *pattern;
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};
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/* Options for the bad block table descriptors */
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/* The number of bits used per block in the bbt on the device */
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#define NAND_BBT_NRBITS_MSK 0x0000000F
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#define NAND_BBT_1BIT 0x00000001
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#define NAND_BBT_2BIT 0x00000002
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#define NAND_BBT_4BIT 0x00000004
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#define NAND_BBT_8BIT 0x00000008
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/* The bad block table is in the last good block of the device */
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#define NAND_BBT_LASTBLOCK 0x00000010
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/* The bbt is at the given page, else we must scan for the bbt */
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#define NAND_BBT_ABSPAGE 0x00000020
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/* The bbt is at the given page, else we must scan for the bbt */
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#define NAND_BBT_SEARCH 0x00000040
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/* bbt is stored per chip on multichip devices */
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#define NAND_BBT_PERCHIP 0x00000080
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/* bbt has a version counter at offset veroffs */
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#define NAND_BBT_VERSION 0x00000100
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/* Create a bbt if none axists */
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#define NAND_BBT_CREATE 0x00000200
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/* Search good / bad pattern through all pages of a block */
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#define NAND_BBT_SCANALLPAGES 0x00000400
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/* Scan block empty during good / bad block scan */
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#define NAND_BBT_SCANEMPTY 0x00000800
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/* Write bbt if neccecary */
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#define NAND_BBT_WRITE 0x00001000
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/* Read and write back block contents when writing bbt */
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#define NAND_BBT_SAVECONTENT 0x00002000
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/* Search good / bad pattern on the first and the second page */
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#define NAND_BBT_SCAN2NDPAGE 0x00004000
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/* The maximum number of blocks to scan for a bbt */
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#define NAND_BBT_SCAN_MAXBLOCKS 4
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extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
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extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
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extern int nand_default_bbt(struct mtd_info *mtd);
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extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
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extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
|
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int allowbbt);
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extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
|
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size_t * retlen, uint8_t * buf);
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|
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/*
|
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* Constants for oob configuration
|
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*/
|
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#define NAND_SMALL_BADBLOCK_POS 5
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#define NAND_LARGE_BADBLOCK_POS 0
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|
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/**
|
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* struct platform_nand_chip - chip level device structure
|
|
*
|
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* @nr_chips: max. number of chips to scan for
|
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* @chip_offs: chip number offset
|
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* @nr_partitions: number of partitions pointed to by partitions (or zero)
|
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* @partitions: mtd partition list
|
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* @chip_delay: R/B delay value in us
|
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* @options: Option flags, e.g. 16bit buswidth
|
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* @ecclayout: ecc layout info structure
|
|
* @priv: hardware controller specific settings
|
|
*/
|
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struct platform_nand_chip {
|
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int nr_chips;
|
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int chip_offset;
|
|
int nr_partitions;
|
|
struct mtd_partition *partitions;
|
|
struct nand_ecclayout *ecclayout;
|
|
int chip_delay;
|
|
unsigned int options;
|
|
void *priv;
|
|
};
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|
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/**
|
|
* struct platform_nand_ctrl - controller level device structure
|
|
*
|
|
* @hwcontrol: platform specific hardware control structure
|
|
* @dev_ready: platform specific function to read ready/busy pin
|
|
* @select_chip: platform specific chip select function
|
|
* @priv_data: private data to transport driver specific settings
|
|
*
|
|
* All fields are optional and depend on the hardware driver requirements
|
|
*/
|
|
struct platform_nand_ctrl {
|
|
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
|
|
int (*dev_ready)(struct mtd_info *mtd);
|
|
void (*select_chip)(struct mtd_info *mtd, int chip);
|
|
void *priv;
|
|
};
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|
|
/* Some helpers to access the data structures */
|
|
static inline
|
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struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
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|
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return chip->priv;
|
|
}
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#endif /* __LINUX_MTD_NAND_H */
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