forked from luck/tmp_suning_uos_patched
250 lines
6.5 KiB
C
250 lines
6.5 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* Copyright (C) 2003 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Setting up the clock on the MIPS boards.
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*/
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/sched.h>
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#include <linux/time.h>
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#include <linux/spinlock.h>
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#include <linux/mc146818rtc.h>
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#include <asm/time.h>
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#include <asm/mipsregs.h>
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#include <asm/ptrace.h>
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#include <asm/it8172/it8172.h>
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#include <asm/it8172/it8172_int.h>
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#include <asm/debug.h>
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#define IT8172_RTC_ADR_REG (IT8172_PCI_IO_BASE + IT_RTC_BASE)
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#define IT8172_RTC_DAT_REG (IT8172_RTC_ADR_REG + 1)
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#define IT8172_RTC_CENTURY_REG (IT8172_PCI_IO_BASE + IT_RTC_CENTURY)
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static volatile char *rtc_adr_reg = (char*)KSEG1ADDR(IT8172_RTC_ADR_REG);
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static volatile char *rtc_dat_reg = (char*)KSEG1ADDR(IT8172_RTC_DAT_REG);
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static volatile char *rtc_century_reg = (char*)KSEG1ADDR(IT8172_RTC_CENTURY_REG);
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unsigned char it8172_rtc_read_data(unsigned long addr)
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{
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unsigned char retval;
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*rtc_adr_reg = addr;
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retval = *rtc_dat_reg;
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return retval;
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}
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void it8172_rtc_write_data(unsigned char data, unsigned long addr)
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{
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*rtc_adr_reg = addr;
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*rtc_dat_reg = data;
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}
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#undef CMOS_READ
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#undef CMOS_WRITE
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#define CMOS_READ(addr) it8172_rtc_read_data(addr)
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#define CMOS_WRITE(data, addr) it8172_rtc_write_data(data, addr)
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static unsigned char saved_control; /* remember rtc control reg */
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static inline int rtc_24h(void) { return saved_control & RTC_24H; }
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static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; }
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static inline unsigned char
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bin_to_hw(unsigned char c)
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{
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if (rtc_dm_binary())
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return c;
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else
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return ((c/10) << 4) + (c%10);
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}
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static inline unsigned char
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hw_to_bin(unsigned char c)
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{
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if (rtc_dm_binary())
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return c;
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else
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return (c>>4)*10 + (c &0xf);
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}
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/* 0x80 bit indicates pm in 12-hour format */
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static inline unsigned char
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hour_bin_to_hw(unsigned char c)
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{
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if (rtc_24h())
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return bin_to_hw(c);
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if (c >= 12)
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return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */
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else
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return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */
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}
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static inline unsigned char
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hour_hw_to_bin(unsigned char c)
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{
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unsigned char tmp = hw_to_bin(c&0x3f);
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if (rtc_24h())
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return tmp;
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if (c & 0x80)
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return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */
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else
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return (tmp==12)?0:tmp; /* 12am is 0 */
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}
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static unsigned long r4k_offset; /* Amount to increment compare reg each time */
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static unsigned long r4k_cur; /* What counter should be at next timer irq */
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extern unsigned int mips_hpt_frequency;
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/*
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* Figure out the r4k offset, the amount to increment the compare
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* register for each time tick.
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* Use the RTC to calculate offset.
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*/
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static unsigned long __init cal_r4koff(void)
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{
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unsigned int flags;
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local_irq_save(flags);
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/* Start counter exactly on falling edge of update flag */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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/* Start r4k counter. */
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write_c0_count(0);
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/* Read counter exactly on falling edge of update flag */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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mips_hpt_frequency = read_c0_count();
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/* restore interrupts */
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local_irq_restore(flags);
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return (mips_hpt_frequency / HZ);
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}
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static unsigned long
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it8172_rtc_get_time(void)
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{
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unsigned int year, mon, day, hour, min, sec;
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unsigned int flags;
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/* avoid update-in-progress. */
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for (;;) {
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local_irq_save(flags);
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if (! (CMOS_READ(RTC_REG_A) & RTC_UIP))
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break;
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/* don't hold intr closed all the time */
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local_irq_restore(flags);
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}
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/* Read regs. */
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sec = hw_to_bin(CMOS_READ(RTC_SECONDS));
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min = hw_to_bin(CMOS_READ(RTC_MINUTES));
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hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS));
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day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH));
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mon = hw_to_bin(CMOS_READ(RTC_MONTH));
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year = hw_to_bin(CMOS_READ(RTC_YEAR)) +
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hw_to_bin(*rtc_century_reg) * 100;
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/* restore interrupts */
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local_irq_restore(flags);
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return mktime(year, mon, day, hour, min, sec);
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}
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static int
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it8172_rtc_set_time(unsigned long t)
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{
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struct rtc_time tm;
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unsigned int flags;
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/* convert */
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to_tm(t, &tm);
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/* avoid update-in-progress. */
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for (;;) {
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local_irq_save(flags);
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if (! (CMOS_READ(RTC_REG_A) & RTC_UIP))
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break;
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/* don't hold intr closed all the time */
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local_irq_restore(flags);
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}
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*rtc_century_reg = bin_to_hw(tm.tm_year/100);
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CMOS_WRITE(bin_to_hw(tm.tm_sec), RTC_SECONDS);
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CMOS_WRITE(bin_to_hw(tm.tm_min), RTC_MINUTES);
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CMOS_WRITE(hour_bin_to_hw(tm.tm_hour), RTC_HOURS);
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CMOS_WRITE(bin_to_hw(tm.tm_mday), RTC_DAY_OF_MONTH);
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CMOS_WRITE(bin_to_hw(tm.tm_mon+1), RTC_MONTH); /* tm_mon starts from 0 */
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CMOS_WRITE(bin_to_hw(tm.tm_year%100), RTC_YEAR);
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/* restore interrupts */
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local_irq_restore(flags);
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return 0;
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}
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void __init it8172_time_init(void)
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{
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unsigned int est_freq, flags;
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local_irq_save(flags);
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saved_control = CMOS_READ(RTC_CONTROL);
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printk("calculating r4koff... ");
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r4k_offset = cal_r4koff();
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printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
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est_freq = 2*r4k_offset*HZ;
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est_freq += 5000; /* round */
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est_freq -= est_freq%10000;
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printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
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(est_freq%1000000)*100/1000000);
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local_irq_restore(flags);
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rtc_mips_get_time = it8172_rtc_get_time;
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rtc_mips_set_time = it8172_rtc_set_time;
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}
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#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
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void __init plat_timer_setup(struct irqaction *irq)
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{
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puts("timer_setup\n");
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put32(NR_IRQS);
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puts("");
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/* we are using the cpu counter for timer interrupts */
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setup_irq(MIPS_CPU_TIMER_IRQ, irq);
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/* to generate the first timer interrupt */
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r4k_cur = (read_c0_count() + r4k_offset);
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write_c0_compare(r4k_cur);
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set_c0_status(ALLINTS);
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}
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