forked from luck/tmp_suning_uos_patched
c7995bcb36
When specifying weim child devices, there is a risk that more than
one timing setting is specified for the same chip select.
The driver cannot support such a configuration.
In case of conflict, this patch will print a warning to the log,
and will ignore the child node in question.
In this example, node acme@1 will be ignored, as it tries to modify
timing settings for CS0:
&weim {
acme@0 {
compatible = "acme,whatever";
reg = <0 0 0x100>;
fsl,weim-cs-timing = <something>;
};
acme@1 {
compatible = "acme,whatnot";
reg = <0 0x500 0x100>;
fsl,weim-cs-timing = <something else>;
};
};
However in this example, the driver will be happy:
&weim {
acme@0 {
compatible = "acme,whatever";
reg = <0 0 0x100>;
fsl,weim-cs-timing = <something>;
};
acme@1 {
compatible = "acme,whatnot";
reg = <0 0x500 0x100>;
fsl,weim-cs-timing = <something>;
};
};
Signed-off-by: Sven Van Asbroeck <TheSven73@googlemail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
263 lines
6.3 KiB
C
263 lines
6.3 KiB
C
/*
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* EIM driver for Freescale's i.MX chips
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*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/regmap.h>
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struct imx_weim_devtype {
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unsigned int cs_count;
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unsigned int cs_regs_count;
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unsigned int cs_stride;
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};
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static const struct imx_weim_devtype imx1_weim_devtype = {
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.cs_count = 6,
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.cs_regs_count = 2,
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.cs_stride = 0x08,
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};
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static const struct imx_weim_devtype imx27_weim_devtype = {
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.cs_count = 6,
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.cs_regs_count = 3,
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.cs_stride = 0x10,
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};
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static const struct imx_weim_devtype imx50_weim_devtype = {
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.cs_count = 4,
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.cs_regs_count = 6,
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.cs_stride = 0x18,
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};
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static const struct imx_weim_devtype imx51_weim_devtype = {
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.cs_count = 6,
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.cs_regs_count = 6,
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.cs_stride = 0x18,
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};
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#define MAX_CS_REGS_COUNT 6
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#define MAX_CS_COUNT 6
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#define OF_REG_SIZE 3
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struct cs_timing {
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bool is_applied;
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u32 regs[MAX_CS_REGS_COUNT];
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};
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struct cs_timing_state {
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struct cs_timing cs[MAX_CS_COUNT];
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};
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static const struct of_device_id weim_id_table[] = {
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/* i.MX1/21 */
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{ .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
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/* i.MX25/27/31/35 */
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{ .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
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/* i.MX50/53/6Q */
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{ .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
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{ .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
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/* i.MX51 */
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{ .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
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{ }
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};
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MODULE_DEVICE_TABLE(of, weim_id_table);
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static int __init imx_weim_gpr_setup(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct property *prop;
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const __be32 *p;
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struct regmap *gpr;
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u32 gprvals[4] = {
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05, /* CS0(128M) CS1(0M) CS2(0M) CS3(0M) */
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033, /* CS0(64M) CS1(64M) CS2(0M) CS3(0M) */
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0113, /* CS0(64M) CS1(32M) CS2(32M) CS3(0M) */
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01111, /* CS0(32M) CS1(32M) CS2(32M) CS3(32M) */
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};
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u32 gprval = 0;
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u32 val;
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int cs = 0;
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int i = 0;
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gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr");
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if (IS_ERR(gpr)) {
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dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n");
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return 0;
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}
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of_property_for_each_u32(np, "ranges", prop, p, val) {
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if (i % 4 == 0) {
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cs = val;
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} else if (i % 4 == 3 && val) {
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val = (val / SZ_32M) | 1;
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gprval |= val << cs * 3;
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}
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i++;
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}
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if (i == 0 || i % 4)
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goto err;
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for (i = 0; i < ARRAY_SIZE(gprvals); i++) {
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if (gprval == gprvals[i]) {
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/* Found it. Set up IOMUXC_GPR1[11:0] with it. */
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regmap_update_bits(gpr, IOMUXC_GPR1, 0xfff, gprval);
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return 0;
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}
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}
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err:
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dev_err(&pdev->dev, "Invalid 'ranges' configuration\n");
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return -EINVAL;
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}
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/* Parse and set the timing for this device. */
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static int __init weim_timing_setup(struct device *dev,
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struct device_node *np, void __iomem *base,
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const struct imx_weim_devtype *devtype,
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struct cs_timing_state *ts)
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{
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u32 cs_idx, value[MAX_CS_REGS_COUNT];
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int i, ret;
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int reg_idx, num_regs;
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struct cs_timing *cst;
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if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT))
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return -EINVAL;
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if (WARN_ON(devtype->cs_count > MAX_CS_COUNT))
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return -EINVAL;
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ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
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value, devtype->cs_regs_count);
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if (ret)
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return ret;
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/*
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* the child node's "reg" property may contain multiple address ranges,
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* extract the chip select for each.
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*/
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num_regs = of_property_count_elems_of_size(np, "reg", OF_REG_SIZE);
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if (num_regs < 0)
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return num_regs;
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if (!num_regs)
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return -EINVAL;
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for (reg_idx = 0; reg_idx < num_regs; reg_idx++) {
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/* get the CS index from this child node's "reg" property. */
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ret = of_property_read_u32_index(np, "reg",
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reg_idx * OF_REG_SIZE, &cs_idx);
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if (ret)
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break;
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if (cs_idx >= devtype->cs_count)
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return -EINVAL;
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/* prevent re-configuring a CS that's already been configured */
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cst = &ts->cs[cs_idx];
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if (cst->is_applied && memcmp(value, cst->regs,
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devtype->cs_regs_count * sizeof(u32))) {
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dev_err(dev, "fsl,weim-cs-timing conflict on %pOF", np);
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return -EINVAL;
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}
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/* set the timing for WEIM */
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for (i = 0; i < devtype->cs_regs_count; i++)
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writel(value[i],
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base + cs_idx * devtype->cs_stride + i * 4);
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if (!cst->is_applied) {
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cst->is_applied = true;
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memcpy(cst->regs, value,
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devtype->cs_regs_count * sizeof(u32));
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}
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}
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return 0;
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}
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static int __init weim_parse_dt(struct platform_device *pdev,
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void __iomem *base)
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{
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const struct of_device_id *of_id = of_match_device(weim_id_table,
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&pdev->dev);
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const struct imx_weim_devtype *devtype = of_id->data;
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struct device_node *child;
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int ret, have_child = 0;
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struct cs_timing_state ts = {};
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if (devtype == &imx50_weim_devtype) {
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ret = imx_weim_gpr_setup(pdev);
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if (ret)
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return ret;
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}
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for_each_available_child_of_node(pdev->dev.of_node, child) {
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ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts);
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if (ret)
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dev_warn(&pdev->dev, "%pOF set timing failed.\n",
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child);
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else
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have_child = 1;
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}
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if (have_child)
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ret = of_platform_default_populate(pdev->dev.of_node,
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NULL, &pdev->dev);
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if (ret)
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dev_err(&pdev->dev, "%pOF fail to create devices.\n",
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pdev->dev.of_node);
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return ret;
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}
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static int __init weim_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct clk *clk;
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void __iomem *base;
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int ret;
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/* get the resource */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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/* get the clock */
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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/* parse the device node */
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ret = weim_parse_dt(pdev, base);
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if (ret)
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clk_disable_unprepare(clk);
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else
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dev_info(&pdev->dev, "Driver registered.\n");
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return ret;
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}
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static struct platform_driver weim_driver = {
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.driver = {
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.name = "imx-weim",
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.of_match_table = weim_id_table,
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},
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};
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module_platform_driver_probe(weim_driver, weim_probe);
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MODULE_AUTHOR("Freescale Semiconductor Inc.");
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MODULE_DESCRIPTION("i.MX EIM Controller Driver");
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MODULE_LICENSE("GPL");
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