forked from luck/tmp_suning_uos_patched
f7225a832d
The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
73 lines
2.8 KiB
C
73 lines
2.8 KiB
C
/*
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* BSD LICENSE
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*
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* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _CLOCK_BCM_NS2_H
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#define _CLOCK_BCM_NS2_H
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/* GENPLL SCR clock channel ID */
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#define BCM_NS2_GENPLL_SCR 0
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#define BCM_NS2_GENPLL_SCR_SCR_CLK 1
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#define BCM_NS2_GENPLL_SCR_FS_CLK 2
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#define BCM_NS2_GENPLL_SCR_AUDIO_CLK 3
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#define BCM_NS2_GENPLL_SCR_CH3_UNUSED 4
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#define BCM_NS2_GENPLL_SCR_CH4_UNUSED 5
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#define BCM_NS2_GENPLL_SCR_CH5_UNUSED 6
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/* GENPLL SW clock channel ID */
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#define BCM_NS2_GENPLL_SW 0
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#define BCM_NS2_GENPLL_SW_RPE_CLK 1
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#define BCM_NS2_GENPLL_SW_250_CLK 2
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#define BCM_NS2_GENPLL_SW_NIC_CLK 3
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#define BCM_NS2_GENPLL_SW_CHIMP_CLK 4
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#define BCM_NS2_GENPLL_SW_PORT_CLK 5
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#define BCM_NS2_GENPLL_SW_SDIO_CLK 6
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/* LCPLL DDR clock channel ID */
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#define BCM_NS2_LCPLL_DDR 0
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#define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK 1
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#define BCM_NS2_LCPLL_DDR_DDR_CLK 2
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#define BCM_NS2_LCPLL_DDR_CH2_UNUSED 3
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#define BCM_NS2_LCPLL_DDR_CH3_UNUSED 4
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#define BCM_NS2_LCPLL_DDR_CH4_UNUSED 5
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#define BCM_NS2_LCPLL_DDR_CH5_UNUSED 6
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/* LCPLL PORTS clock channel ID */
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#define BCM_NS2_LCPLL_PORTS 0
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#define BCM_NS2_LCPLL_PORTS_WAN_CLK 1
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#define BCM_NS2_LCPLL_PORTS_RGMII_CLK 2
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#define BCM_NS2_LCPLL_PORTS_CH2_UNUSED 3
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#define BCM_NS2_LCPLL_PORTS_CH3_UNUSED 4
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#define BCM_NS2_LCPLL_PORTS_CH4_UNUSED 5
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#define BCM_NS2_LCPLL_PORTS_CH5_UNUSED 6
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#endif /* _CLOCK_BCM_NS2_H */
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