forked from luck/tmp_suning_uos_patched
3476195651
majority of the diff is the normal collection of driver additions for new SoCs
and non-critical clk data fixes and updates. The framework must be middle aged.
The two biggest directories in the diffstat show that the Qualcomm and Unisoc
support added a handful of big drivers for new SoCs but that's not really the
whole story because those new drivers tend to add large numbers of lines of clk
data. There's a handful of AT91 clk drivers added this time around too and a
bunch of improvements to drivers like the i.MX driver. All around lots of
updates and fixes in various clk drivers which is good to see.
The core framework has only one real major change which has been baking in next
for the past couple months. It fixes the framework so that it stops caching a
clk's phase when the phase clk_op returns an error. Before this change we would
consider some negative errno as a phase and that just doesn't make sense.
Core:
- Don't show clk phase when it is invalid
New Drivers:
- Add support for Unisoc SC9863A clks
- Qualcomm SM8250 RPMh and MSM8976 RPM clks
- Qualcomm SM8250 Global Clock Controller (GCC) support
- Qualcomm SC7180 Modem Clock Controller (MSS CC) support
- EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs
- Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs
Updates:
- GPU GX GDSC support on Qualcomm sc7180
- Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers
- A series from Anson to convert i.MX8 clock bindings to json-schema
- Update i.MX pll14xx driver to include new frequency entries for pll1443x table,
and return error for invalid PLL type
- Add missing of_node_put() call for a number of i.MX clock drivers
- Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already
have the flag on its child cpu clock
- Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL
via CORE_SEL slice, and source from A53 CCM clk root when we need to
change ARM PLL frequency. Thus, we can support core running above
1GHz safely
- Update i.MX pfdv2 driver to check zero rate and use determine_rate for
getting the best rate
- Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for imx7d
- Remove PMC clks from Tegra clk driver
- Improved clock/reset handling for the Renesas R-Car USB2 Clock Selector
- Conversion to json-schema of the Renesas CPG/MSSR DT bindings
- Add Crypto clocks on Renesas R-Car M3-W/W+, M3-N, E3, and D3
- Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car H3, M3-W/W+, and M3-N
- Update Amlogic audio clock gate hierarchy for meson8 and gxbb
- Update Amlogic g12a spicc clock sources
- Support for Ingenic X1000 TCU clks
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"There's not much to see in the core framework this time around.
Instead the majority of the diff is the normal collection of driver
additions for new SoCs and non-critical clk data fixes and updates.
The framework must be middle aged.
The two biggest directories in the diffstat show that the Qualcomm and
Unisoc support added a handful of big drivers for new SoCs but that's
not really the whole story because those new drivers tend to add large
numbers of lines of clk data. There's a handful of AT91 clk drivers
added this time around too and a bunch of improvements to drivers like
the i.MX driver. All around lots of updates and fixes in various clk
drivers which is good to see.
The core framework has only one real major change which has been
baking in next for the past couple months. It fixes the framework so
that it stops caching a clk's phase when the phase clk_op returns an
error. Before this change we would consider some negative errno as a
phase and that just doesn't make sense.
Core:
- Don't show clk phase when it is invalid
New Drivers:
- Add support for Unisoc SC9863A clks
- Qualcomm SM8250 RPMh and MSM8976 RPM clks
- Qualcomm SM8250 Global Clock Controller (GCC) support
- Qualcomm SC7180 Modem Clock Controller (MSS CC) support
- EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs
- Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and
at91sam9g45 SoCs
Updates:
- GPU GX GDSC support on Qualcomm sc7180
- Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers
- A series from Anson to convert i.MX8 clock bindings to json-schema
- Update i.MX pll14xx driver to include new frequency entries for
pll1443x table, and return error for invalid PLL type
- Add missing of_node_put() call for a number of i.MX clock drivers
- Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already
have the flag on its child cpu clock
- Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL
via CORE_SEL slice, and source from A53 CCM clk root when we need
to change ARM PLL frequency. Thus, we can support core running
above 1GHz safely
- Update i.MX pfdv2 driver to check zero rate and use determine_rate
for getting the best rate
- Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for
imx7d
- Remove PMC clks from Tegra clk driver
- Improved clock/reset handling for the Renesas R-Car USB2 Clock
Selector
- Conversion to json-schema of the Renesas CPG/MSSR DT bindings
- Add Crypto clocks on Renesas R-Car M3-W/W+, M3-N, E3, and D3
- Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car H3, M3-W/W+, and
M3-N
- Update Amlogic audio clock gate hierarchy for meson8 and gxbb
- Update Amlogic g12a spicc clock sources
- Support for Ingenic X1000 TCU clks"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (146 commits)
clk: sprd: fix to get a correct ibias of pll
dt-bindings: imx8mm-clock: Fix the file path
dt-bindings: imx8mq-clock: Fix the file path
clk: qcom: rpmh: Drop unnecessary semicolons
clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd()
clk: tegra: Use NULL for pointer initialization
clk: sprd: add clocks support for SC9863A
clk: sprd: support to get regmap from parent node
clk: sprd: Add macros for referencing parents without strings
clk: sprd: Add dt-bindings include file for SC9863A
dt-bindings: clk: sprd: add bindings for sc9863a clock controller
dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific
clk: sprd: add gate for pll clocks
MAINTAINERS: dt: update reference for arm-integrator.txt
clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks
clk: mmp2: Add clock for fifth SD HCI on MMP3
dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3
clk: mmp2: Add clocks for the thermal sensors
dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors
clk: mmp2: add the GPU clocks
...
240 lines
7.5 KiB
C
240 lines
7.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2018-2019 NXP
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
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#define __DT_BINDINGS_CLOCK_IMX8MN_H
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#define IMX8MN_CLK_DUMMY 0
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#define IMX8MN_CLK_32K 1
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#define IMX8MN_CLK_24M 2
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#define IMX8MN_OSC_HDMI_CLK 3
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#define IMX8MN_CLK_EXT1 4
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#define IMX8MN_CLK_EXT2 5
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#define IMX8MN_CLK_EXT3 6
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#define IMX8MN_CLK_EXT4 7
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#define IMX8MN_AUDIO_PLL1_REF_SEL 8
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#define IMX8MN_AUDIO_PLL2_REF_SEL 9
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#define IMX8MN_VIDEO_PLL1_REF_SEL 10
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#define IMX8MN_DRAM_PLL_REF_SEL 11
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#define IMX8MN_GPU_PLL_REF_SEL 12
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#define IMX8MN_VPU_PLL_REF_SEL 13
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#define IMX8MN_ARM_PLL_REF_SEL 14
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#define IMX8MN_SYS_PLL1_REF_SEL 15
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#define IMX8MN_SYS_PLL2_REF_SEL 16
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#define IMX8MN_SYS_PLL3_REF_SEL 17
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#define IMX8MN_AUDIO_PLL1 18
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#define IMX8MN_AUDIO_PLL2 19
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#define IMX8MN_VIDEO_PLL1 20
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#define IMX8MN_DRAM_PLL 21
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#define IMX8MN_GPU_PLL 22
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#define IMX8MN_VPU_PLL 23
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#define IMX8MN_ARM_PLL 24
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#define IMX8MN_SYS_PLL1 25
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#define IMX8MN_SYS_PLL2 26
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#define IMX8MN_SYS_PLL3 27
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#define IMX8MN_AUDIO_PLL1_BYPASS 28
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#define IMX8MN_AUDIO_PLL2_BYPASS 29
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#define IMX8MN_VIDEO_PLL1_BYPASS 30
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#define IMX8MN_DRAM_PLL_BYPASS 31
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#define IMX8MN_GPU_PLL_BYPASS 32
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#define IMX8MN_VPU_PLL_BYPASS 33
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#define IMX8MN_ARM_PLL_BYPASS 34
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#define IMX8MN_SYS_PLL1_BYPASS 35
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#define IMX8MN_SYS_PLL2_BYPASS 36
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#define IMX8MN_SYS_PLL3_BYPASS 37
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#define IMX8MN_AUDIO_PLL1_OUT 38
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#define IMX8MN_AUDIO_PLL2_OUT 39
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#define IMX8MN_VIDEO_PLL1_OUT 40
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#define IMX8MN_DRAM_PLL_OUT 41
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#define IMX8MN_GPU_PLL_OUT 42
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#define IMX8MN_VPU_PLL_OUT 43
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#define IMX8MN_ARM_PLL_OUT 44
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#define IMX8MN_SYS_PLL1_OUT 45
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#define IMX8MN_SYS_PLL2_OUT 46
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#define IMX8MN_SYS_PLL3_OUT 47
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#define IMX8MN_SYS_PLL1_40M 48
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#define IMX8MN_SYS_PLL1_80M 49
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#define IMX8MN_SYS_PLL1_100M 50
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#define IMX8MN_SYS_PLL1_133M 51
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#define IMX8MN_SYS_PLL1_160M 52
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#define IMX8MN_SYS_PLL1_200M 53
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#define IMX8MN_SYS_PLL1_266M 54
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#define IMX8MN_SYS_PLL1_400M 55
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#define IMX8MN_SYS_PLL1_800M 56
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#define IMX8MN_SYS_PLL2_50M 57
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#define IMX8MN_SYS_PLL2_100M 58
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#define IMX8MN_SYS_PLL2_125M 59
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#define IMX8MN_SYS_PLL2_166M 60
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#define IMX8MN_SYS_PLL2_200M 61
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#define IMX8MN_SYS_PLL2_250M 62
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#define IMX8MN_SYS_PLL2_333M 63
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#define IMX8MN_SYS_PLL2_500M 64
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#define IMX8MN_SYS_PLL2_1000M 65
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/* CORE CLOCK ROOT */
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#define IMX8MN_CLK_A53_SRC 66
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#define IMX8MN_CLK_GPU_CORE_SRC 67
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#define IMX8MN_CLK_GPU_SHADER_SRC 68
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#define IMX8MN_CLK_A53_CG 69
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#define IMX8MN_CLK_GPU_CORE_CG 70
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#define IMX8MN_CLK_GPU_SHADER_CG 71
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#define IMX8MN_CLK_A53_DIV 72
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#define IMX8MN_CLK_GPU_CORE_DIV 73
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#define IMX8MN_CLK_GPU_SHADER_DIV 74
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/* BUS CLOCK ROOT */
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#define IMX8MN_CLK_MAIN_AXI 75
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#define IMX8MN_CLK_ENET_AXI 76
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#define IMX8MN_CLK_NAND_USDHC_BUS 77
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#define IMX8MN_CLK_DISP_AXI 78
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#define IMX8MN_CLK_DISP_APB 79
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#define IMX8MN_CLK_USB_BUS 80
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#define IMX8MN_CLK_GPU_AXI 81
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#define IMX8MN_CLK_GPU_AHB 82
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#define IMX8MN_CLK_NOC 83
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#define IMX8MN_CLK_AHB 84
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#define IMX8MN_CLK_AUDIO_AHB 85
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/* IPG CLOCK ROOT */
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#define IMX8MN_CLK_IPG_ROOT 86
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#define IMX8MN_CLK_IPG_AUDIO_ROOT 87
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/* IP */
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#define IMX8MN_CLK_DRAM_CORE 88
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#define IMX8MN_CLK_DRAM_ALT 89
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#define IMX8MN_CLK_DRAM_APB 90
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#define IMX8MN_CLK_DRAM_ALT_ROOT 91
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#define IMX8MN_CLK_DISP_PIXEL 92
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#define IMX8MN_CLK_SAI2 93
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#define IMX8MN_CLK_SAI3 94
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#define IMX8MN_CLK_SAI5 95
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#define IMX8MN_CLK_SAI6 96
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#define IMX8MN_CLK_SPDIF1 97
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#define IMX8MN_CLK_ENET_REF 98
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#define IMX8MN_CLK_ENET_TIMER 99
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#define IMX8MN_CLK_ENET_PHY_REF 100
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#define IMX8MN_CLK_NAND 101
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#define IMX8MN_CLK_QSPI 102
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#define IMX8MN_CLK_USDHC1 103
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#define IMX8MN_CLK_USDHC2 104
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#define IMX8MN_CLK_I2C1 105
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#define IMX8MN_CLK_I2C2 106
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#define IMX8MN_CLK_I2C3 107
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#define IMX8MN_CLK_I2C4 108
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#define IMX8MN_CLK_UART1 109
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#define IMX8MN_CLK_UART2 110
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#define IMX8MN_CLK_UART3 111
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#define IMX8MN_CLK_UART4 112
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#define IMX8MN_CLK_USB_CORE_REF 113
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#define IMX8MN_CLK_USB_PHY_REF 114
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#define IMX8MN_CLK_ECSPI1 115
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#define IMX8MN_CLK_ECSPI2 116
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#define IMX8MN_CLK_PWM1 117
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#define IMX8MN_CLK_PWM2 118
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#define IMX8MN_CLK_PWM3 119
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#define IMX8MN_CLK_PWM4 120
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#define IMX8MN_CLK_WDOG 121
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#define IMX8MN_CLK_WRCLK 122
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#define IMX8MN_CLK_CLKO1 123
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#define IMX8MN_CLK_CLKO2 124
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#define IMX8MN_CLK_DSI_CORE 125
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#define IMX8MN_CLK_DSI_PHY_REF 126
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#define IMX8MN_CLK_DSI_DBI 127
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#define IMX8MN_CLK_USDHC3 128
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#define IMX8MN_CLK_CAMERA_PIXEL 129
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#define IMX8MN_CLK_CSI1_PHY_REF 130
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#define IMX8MN_CLK_CSI2_PHY_REF 131
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#define IMX8MN_CLK_CSI2_ESC 132
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#define IMX8MN_CLK_ECSPI3 133
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#define IMX8MN_CLK_PDM 134
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#define IMX8MN_CLK_SAI7 135
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#define IMX8MN_CLK_ECSPI1_ROOT 136
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#define IMX8MN_CLK_ECSPI2_ROOT 137
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#define IMX8MN_CLK_ECSPI3_ROOT 138
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#define IMX8MN_CLK_ENET1_ROOT 139
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#define IMX8MN_CLK_GPIO1_ROOT 140
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#define IMX8MN_CLK_GPIO2_ROOT 141
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#define IMX8MN_CLK_GPIO3_ROOT 142
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#define IMX8MN_CLK_GPIO4_ROOT 143
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#define IMX8MN_CLK_GPIO5_ROOT 144
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#define IMX8MN_CLK_I2C1_ROOT 145
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#define IMX8MN_CLK_I2C2_ROOT 146
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#define IMX8MN_CLK_I2C3_ROOT 147
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#define IMX8MN_CLK_I2C4_ROOT 148
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#define IMX8MN_CLK_MU_ROOT 149
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#define IMX8MN_CLK_OCOTP_ROOT 150
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#define IMX8MN_CLK_PWM1_ROOT 151
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#define IMX8MN_CLK_PWM2_ROOT 152
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#define IMX8MN_CLK_PWM3_ROOT 153
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#define IMX8MN_CLK_PWM4_ROOT 154
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#define IMX8MN_CLK_QSPI_ROOT 155
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#define IMX8MN_CLK_NAND_ROOT 156
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#define IMX8MN_CLK_SAI2_ROOT 157
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#define IMX8MN_CLK_SAI2_IPG 158
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#define IMX8MN_CLK_SAI3_ROOT 159
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#define IMX8MN_CLK_SAI3_IPG 160
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#define IMX8MN_CLK_SAI5_ROOT 161
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#define IMX8MN_CLK_SAI5_IPG 162
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#define IMX8MN_CLK_SAI6_ROOT 163
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#define IMX8MN_CLK_SAI6_IPG 164
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#define IMX8MN_CLK_SAI7_ROOT 165
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#define IMX8MN_CLK_SAI7_IPG 166
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#define IMX8MN_CLK_SDMA1_ROOT 167
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#define IMX8MN_CLK_SDMA2_ROOT 168
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#define IMX8MN_CLK_UART1_ROOT 169
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#define IMX8MN_CLK_UART2_ROOT 170
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#define IMX8MN_CLK_UART3_ROOT 171
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#define IMX8MN_CLK_UART4_ROOT 172
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#define IMX8MN_CLK_USB1_CTRL_ROOT 173
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#define IMX8MN_CLK_USDHC1_ROOT 174
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#define IMX8MN_CLK_USDHC2_ROOT 175
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#define IMX8MN_CLK_WDOG1_ROOT 176
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#define IMX8MN_CLK_WDOG2_ROOT 177
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#define IMX8MN_CLK_WDOG3_ROOT 178
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#define IMX8MN_CLK_GPU_BUS_ROOT 179
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#define IMX8MN_CLK_ASRC_ROOT 180
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#define IMX8MN_CLK_GPU3D_ROOT 181
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#define IMX8MN_CLK_PDM_ROOT 182
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#define IMX8MN_CLK_PDM_IPG 183
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#define IMX8MN_CLK_DISP_AXI_ROOT 184
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#define IMX8MN_CLK_DISP_APB_ROOT 185
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#define IMX8MN_CLK_DISP_PIXEL_ROOT 186
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#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187
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#define IMX8MN_CLK_USDHC3_ROOT 188
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#define IMX8MN_CLK_SDMA3_ROOT 189
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#define IMX8MN_CLK_TMU_ROOT 190
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#define IMX8MN_CLK_ARM 191
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#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
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#define IMX8MN_CLK_GPU_CORE_ROOT 193
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#define IMX8MN_CLK_GIC 194
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#define IMX8MN_SYS_PLL1_40M_CG 195
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#define IMX8MN_SYS_PLL1_80M_CG 196
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#define IMX8MN_SYS_PLL1_100M_CG 197
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#define IMX8MN_SYS_PLL1_133M_CG 198
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#define IMX8MN_SYS_PLL1_160M_CG 199
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#define IMX8MN_SYS_PLL1_200M_CG 200
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#define IMX8MN_SYS_PLL1_266M_CG 201
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#define IMX8MN_SYS_PLL1_400M_CG 202
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#define IMX8MN_SYS_PLL2_50M_CG 203
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#define IMX8MN_SYS_PLL2_100M_CG 204
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#define IMX8MN_SYS_PLL2_125M_CG 205
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#define IMX8MN_SYS_PLL2_166M_CG 206
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#define IMX8MN_SYS_PLL2_200M_CG 207
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#define IMX8MN_SYS_PLL2_250M_CG 208
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#define IMX8MN_SYS_PLL2_333M_CG 209
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#define IMX8MN_SYS_PLL2_500M_CG 210
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#define IMX8MN_CLK_SNVS_ROOT 211
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#define IMX8MN_CLK_GPU_CORE 212
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#define IMX8MN_CLK_GPU_SHADER 213
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#define IMX8MN_CLK_A53_CORE 214
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#define IMX8MN_CLK_END 215
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#endif
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