forked from luck/tmp_suning_uos_patched
8c18b41b39
This change adds GDSCs, resets and most of the missing clocks to the msm8994 GCC driver. The remaining ones are of local_vote_clk and gate_clk type, which are not yet supported upstream. Also reorder them to match the original downstream driver. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20201005145855.149206-1-konradybcio@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
167 lines
5.4 KiB
C
167 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
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#define _DT_BINDINGS_CLK_MSM_GCC_8994_H
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#define GPLL0_EARLY 0
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#define GPLL0 1
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#define GPLL4_EARLY 2
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#define GPLL4 3
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#define UFS_AXI_CLK_SRC 4
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#define USB30_MASTER_CLK_SRC 5
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 6
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 7
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 8
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 9
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 10
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 11
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 12
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 13
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#define BLSP1_QUP5_I2C_APPS_CLK_SRC 14
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#define BLSP1_QUP5_SPI_APPS_CLK_SRC 15
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#define BLSP1_QUP6_I2C_APPS_CLK_SRC 16
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#define BLSP1_QUP6_SPI_APPS_CLK_SRC 17
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#define BLSP1_UART1_APPS_CLK_SRC 18
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#define BLSP1_UART2_APPS_CLK_SRC 19
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#define BLSP1_UART3_APPS_CLK_SRC 20
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#define BLSP1_UART4_APPS_CLK_SRC 21
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#define BLSP1_UART5_APPS_CLK_SRC 22
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#define BLSP1_UART6_APPS_CLK_SRC 23
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#define BLSP2_QUP1_I2C_APPS_CLK_SRC 24
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#define BLSP2_QUP1_SPI_APPS_CLK_SRC 25
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#define BLSP2_QUP2_I2C_APPS_CLK_SRC 26
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#define BLSP2_QUP2_SPI_APPS_CLK_SRC 27
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#define BLSP2_QUP3_I2C_APPS_CLK_SRC 28
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#define BLSP2_QUP3_SPI_APPS_CLK_SRC 29
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#define BLSP2_QUP4_I2C_APPS_CLK_SRC 30
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#define BLSP2_QUP4_SPI_APPS_CLK_SRC 31
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#define BLSP2_QUP5_I2C_APPS_CLK_SRC 32
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#define BLSP2_QUP5_SPI_APPS_CLK_SRC 33
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#define BLSP2_QUP6_I2C_APPS_CLK_SRC 34
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#define BLSP2_QUP6_SPI_APPS_CLK_SRC 35
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#define BLSP2_UART1_APPS_CLK_SRC 36
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#define BLSP2_UART2_APPS_CLK_SRC 37
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#define BLSP2_UART3_APPS_CLK_SRC 38
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#define BLSP2_UART4_APPS_CLK_SRC 39
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#define BLSP2_UART5_APPS_CLK_SRC 40
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#define BLSP2_UART6_APPS_CLK_SRC 41
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#define GP1_CLK_SRC 42
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#define GP2_CLK_SRC 43
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#define GP3_CLK_SRC 44
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#define PCIE_0_AUX_CLK_SRC 45
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#define PCIE_0_PIPE_CLK_SRC 46
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#define PCIE_1_AUX_CLK_SRC 47
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#define PCIE_1_PIPE_CLK_SRC 48
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#define PDM2_CLK_SRC 49
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#define SDCC1_APPS_CLK_SRC 50
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#define SDCC2_APPS_CLK_SRC 51
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#define SDCC3_APPS_CLK_SRC 52
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#define SDCC4_APPS_CLK_SRC 53
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#define TSIF_REF_CLK_SRC 54
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#define USB30_MOCK_UTMI_CLK_SRC 55
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#define USB3_PHY_AUX_CLK_SRC 56
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#define USB_HS_SYSTEM_CLK_SRC 57
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#define GCC_BLSP1_AHB_CLK 58
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 59
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 60
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 61
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 62
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 63
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 64
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 65
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 66
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#define GCC_BLSP1_QUP5_I2C_APPS_CLK 67
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#define GCC_BLSP1_QUP5_SPI_APPS_CLK 68
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#define GCC_BLSP1_QUP6_I2C_APPS_CLK 69
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#define GCC_BLSP1_QUP6_SPI_APPS_CLK 70
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#define GCC_BLSP1_UART1_APPS_CLK 71
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#define GCC_BLSP1_UART2_APPS_CLK 72
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#define GCC_BLSP1_UART3_APPS_CLK 73
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#define GCC_BLSP1_UART4_APPS_CLK 74
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#define GCC_BLSP1_UART5_APPS_CLK 75
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#define GCC_BLSP1_UART6_APPS_CLK 76
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#define GCC_BLSP2_AHB_CLK 77
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#define GCC_BLSP2_QUP1_I2C_APPS_CLK 78
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#define GCC_BLSP2_QUP1_SPI_APPS_CLK 79
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#define GCC_BLSP2_QUP2_I2C_APPS_CLK 80
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#define GCC_BLSP2_QUP2_SPI_APPS_CLK 81
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#define GCC_BLSP2_QUP3_I2C_APPS_CLK 82
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#define GCC_BLSP2_QUP3_SPI_APPS_CLK 83
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#define GCC_BLSP2_QUP4_I2C_APPS_CLK 84
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#define GCC_BLSP2_QUP4_SPI_APPS_CLK 85
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#define GCC_BLSP2_QUP5_I2C_APPS_CLK 86
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#define GCC_BLSP2_QUP5_SPI_APPS_CLK 87
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#define GCC_BLSP2_QUP6_I2C_APPS_CLK 88
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#define GCC_BLSP2_QUP6_SPI_APPS_CLK 89
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#define GCC_BLSP2_UART1_APPS_CLK 90
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#define GCC_BLSP2_UART2_APPS_CLK 91
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#define GCC_BLSP2_UART3_APPS_CLK 92
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#define GCC_BLSP2_UART4_APPS_CLK 93
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#define GCC_BLSP2_UART5_APPS_CLK 94
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#define GCC_BLSP2_UART6_APPS_CLK 95
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#define GCC_GP1_CLK 96
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#define GCC_GP2_CLK 97
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#define GCC_GP3_CLK 98
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#define GCC_PCIE_0_AUX_CLK 99
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#define GCC_PCIE_0_PIPE_CLK 100
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#define GCC_PCIE_1_AUX_CLK 101
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#define GCC_PCIE_1_PIPE_CLK 102
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#define GCC_PDM2_CLK 103
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#define GCC_SDCC1_APPS_CLK 104
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#define GCC_SDCC2_APPS_CLK 105
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#define GCC_SDCC3_APPS_CLK 106
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#define GCC_SDCC4_APPS_CLK 107
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#define GCC_SYS_NOC_UFS_AXI_CLK 108
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#define GCC_SYS_NOC_USB3_AXI_CLK 109
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#define GCC_TSIF_REF_CLK 110
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#define GCC_UFS_AXI_CLK 111
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#define GCC_UFS_RX_CFG_CLK 112
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#define GCC_UFS_TX_CFG_CLK 113
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#define GCC_USB30_MASTER_CLK 114
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#define GCC_USB30_MOCK_UTMI_CLK 115
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#define GCC_USB3_PHY_AUX_CLK 116
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#define GCC_USB_HS_SYSTEM_CLK 117
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#define GCC_SDCC1_AHB_CLK 118
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#define GCC_LPASS_Q6_AXI_CLK 119
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#define GCC_MSS_Q6_BIMC_AXI_CLK 120
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#define GCC_PCIE_0_CFG_AHB_CLK 121
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#define GCC_PCIE_0_MSTR_AXI_CLK 122
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#define GCC_PCIE_0_SLV_AXI_CLK 123
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#define GCC_PCIE_1_CFG_AHB_CLK 124
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#define GCC_PCIE_1_MSTR_AXI_CLK 125
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#define GCC_PCIE_1_SLV_AXI_CLK 126
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#define GCC_PDM_AHB_CLK 127
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#define GCC_SDCC2_AHB_CLK 128
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#define GCC_SDCC3_AHB_CLK 129
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#define GCC_SDCC4_AHB_CLK 130
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#define GCC_TSIF_AHB_CLK 131
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#define GCC_UFS_AHB_CLK 132
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#define GCC_UFS_RX_SYMBOL_0_CLK 133
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#define GCC_UFS_RX_SYMBOL_1_CLK 134
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#define GCC_UFS_TX_SYMBOL_0_CLK 135
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#define GCC_UFS_TX_SYMBOL_1_CLK 136
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#define GCC_USB2_HS_PHY_SLEEP_CLK 137
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#define GCC_USB30_SLEEP_CLK 138
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#define GCC_USB_HS_AHB_CLK 139
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 140
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/* GDSCs */
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#define PCIE_GDSC 0
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#define PCIE_0_GDSC 1
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#define PCIE_1_GDSC 2
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#define USB30_GDSC 3
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#define UFS_GDSC 4
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/* Resets */
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#define USB3_PHY_RESET 0
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#define USB3PHY_PHY_RESET 1
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#define PCIE_PHY_0_RESET 2
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#define PCIE_PHY_1_RESET 3
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#define QUSB2_PHY_RESET 4
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#endif
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