forked from luck/tmp_suning_uos_patched
d1492bbd47
Add documentation for PMIC7 ADC peripheral. For the PMIC7-type PMICs, ADC peripheral is present in HW for the following PMICs: PMK8350, PM8350, PM8350b, PMR735a and PMR735b. Of these, only the ADC peripheral on PMK8350 is exposed directly to SW. If SW needs to communicate with ADCs on other PMICs, it specifies the PMIC to PMK8350 through the newly added SID register and communication between PMK8350 ADC and other PMIC ADCs is carried out through PBS(Programmable Boot Sequence) at the firmware level. In addition, add definitions for ADC channels and virtual channel definitions (combination of ADC channel number and PMIC SID number) per PMIC, to be used by ADC clients for PMIC7. Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
301 lines
9.1 KiB
C
301 lines
9.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
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#define _DT_BINDINGS_QCOM_SPMI_VADC_H
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/* Voltage ADC channels */
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#define VADC_USBIN 0x00
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#define VADC_DCIN 0x01
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#define VADC_VCHG_SNS 0x02
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#define VADC_SPARE1_03 0x03
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#define VADC_USB_ID_MV 0x04
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#define VADC_VCOIN 0x05
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#define VADC_VBAT_SNS 0x06
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#define VADC_VSYS 0x07
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#define VADC_DIE_TEMP 0x08
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#define VADC_REF_625MV 0x09
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#define VADC_REF_1250MV 0x0a
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#define VADC_CHG_TEMP 0x0b
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#define VADC_SPARE1 0x0c
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#define VADC_SPARE2 0x0d
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#define VADC_GND_REF 0x0e
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#define VADC_VDD_VADC 0x0f
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#define VADC_P_MUX1_1_1 0x10
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#define VADC_P_MUX2_1_1 0x11
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#define VADC_P_MUX3_1_1 0x12
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#define VADC_P_MUX4_1_1 0x13
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#define VADC_P_MUX5_1_1 0x14
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#define VADC_P_MUX6_1_1 0x15
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#define VADC_P_MUX7_1_1 0x16
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#define VADC_P_MUX8_1_1 0x17
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#define VADC_P_MUX9_1_1 0x18
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#define VADC_P_MUX10_1_1 0x19
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#define VADC_P_MUX11_1_1 0x1a
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#define VADC_P_MUX12_1_1 0x1b
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#define VADC_P_MUX13_1_1 0x1c
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#define VADC_P_MUX14_1_1 0x1d
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#define VADC_P_MUX15_1_1 0x1e
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#define VADC_P_MUX16_1_1 0x1f
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#define VADC_P_MUX1_1_3 0x20
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#define VADC_P_MUX2_1_3 0x21
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#define VADC_P_MUX3_1_3 0x22
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#define VADC_P_MUX4_1_3 0x23
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#define VADC_P_MUX5_1_3 0x24
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#define VADC_P_MUX6_1_3 0x25
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#define VADC_P_MUX7_1_3 0x26
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#define VADC_P_MUX8_1_3 0x27
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#define VADC_P_MUX9_1_3 0x28
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#define VADC_P_MUX10_1_3 0x29
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#define VADC_P_MUX11_1_3 0x2a
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#define VADC_P_MUX12_1_3 0x2b
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#define VADC_P_MUX13_1_3 0x2c
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#define VADC_P_MUX14_1_3 0x2d
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#define VADC_P_MUX15_1_3 0x2e
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#define VADC_P_MUX16_1_3 0x2f
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#define VADC_LR_MUX1_BAT_THERM 0x30
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#define VADC_LR_MUX2_BAT_ID 0x31
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#define VADC_LR_MUX3_XO_THERM 0x32
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#define VADC_LR_MUX4_AMUX_THM1 0x33
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#define VADC_LR_MUX5_AMUX_THM2 0x34
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#define VADC_LR_MUX6_AMUX_THM3 0x35
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#define VADC_LR_MUX7_HW_ID 0x36
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#define VADC_LR_MUX8_AMUX_THM4 0x37
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#define VADC_LR_MUX9_AMUX_THM5 0x38
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#define VADC_LR_MUX10_USB_ID 0x39
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#define VADC_AMUX_PU1 0x3a
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#define VADC_AMUX_PU2 0x3b
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#define VADC_LR_MUX3_BUF_XO_THERM 0x3c
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#define VADC_LR_MUX1_PU1_BAT_THERM 0x70
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#define VADC_LR_MUX2_PU1_BAT_ID 0x71
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#define VADC_LR_MUX3_PU1_XO_THERM 0x72
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#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73
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#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74
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#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75
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#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76
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#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77
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#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78
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#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79
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#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c
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#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0
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#define VADC_LR_MUX2_PU2_BAT_ID 0xb1
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#define VADC_LR_MUX3_PU2_XO_THERM 0xb2
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#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3
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#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4
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#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5
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#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6
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#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7
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#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8
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#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9
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#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc
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#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0
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#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1
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#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2
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#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3
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#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4
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#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5
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#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6
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#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7
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#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8
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#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9
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#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc
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/* ADC channels for SPMI PMIC5 */
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#define ADC5_REF_GND 0x00
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#define ADC5_1P25VREF 0x01
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#define ADC5_VREF_VADC 0x02
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#define ADC5_VREF_VADC5_DIV_3 0x82
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#define ADC5_VPH_PWR 0x83
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#define ADC5_VBAT_SNS 0x84
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#define ADC5_VCOIN 0x85
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#define ADC5_DIE_TEMP 0x06
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#define ADC5_USB_IN_I 0x07
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#define ADC5_USB_IN_V_16 0x08
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#define ADC5_CHG_TEMP 0x09
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#define ADC5_BAT_THERM 0x0a
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#define ADC5_BAT_ID 0x0b
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#define ADC5_XO_THERM 0x0c
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#define ADC5_AMUX_THM1 0x0d
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#define ADC5_AMUX_THM2 0x0e
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#define ADC5_AMUX_THM3 0x0f
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#define ADC5_AMUX_THM4 0x10
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#define ADC5_AMUX_THM5 0x11
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#define ADC5_GPIO1 0x12
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#define ADC5_GPIO2 0x13
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#define ADC5_GPIO3 0x14
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#define ADC5_GPIO4 0x15
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#define ADC5_GPIO5 0x16
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#define ADC5_GPIO6 0x17
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#define ADC5_GPIO7 0x18
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#define ADC5_SBUx 0x99
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#define ADC5_MID_CHG_DIV6 0x1e
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#define ADC5_OFF 0xff
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/* 30k pull-up1 */
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#define ADC5_BAT_THERM_30K_PU 0x2a
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#define ADC5_BAT_ID_30K_PU 0x2b
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#define ADC5_XO_THERM_30K_PU 0x2c
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#define ADC5_AMUX_THM1_30K_PU 0x2d
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#define ADC5_AMUX_THM2_30K_PU 0x2e
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#define ADC5_AMUX_THM3_30K_PU 0x2f
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#define ADC5_AMUX_THM4_30K_PU 0x30
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#define ADC5_AMUX_THM5_30K_PU 0x31
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#define ADC5_GPIO1_30K_PU 0x32
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#define ADC5_GPIO2_30K_PU 0x33
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#define ADC5_GPIO3_30K_PU 0x34
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#define ADC5_GPIO4_30K_PU 0x35
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#define ADC5_GPIO5_30K_PU 0x36
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#define ADC5_GPIO6_30K_PU 0x37
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#define ADC5_GPIO7_30K_PU 0x38
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#define ADC5_SBUx_30K_PU 0x39
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/* 100k pull-up2 */
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#define ADC5_BAT_THERM_100K_PU 0x4a
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#define ADC5_BAT_ID_100K_PU 0x4b
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#define ADC5_XO_THERM_100K_PU 0x4c
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#define ADC5_AMUX_THM1_100K_PU 0x4d
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#define ADC5_AMUX_THM2_100K_PU 0x4e
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#define ADC5_AMUX_THM3_100K_PU 0x4f
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#define ADC5_AMUX_THM4_100K_PU 0x50
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#define ADC5_AMUX_THM5_100K_PU 0x51
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#define ADC5_GPIO1_100K_PU 0x52
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#define ADC5_GPIO2_100K_PU 0x53
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#define ADC5_GPIO3_100K_PU 0x54
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#define ADC5_GPIO4_100K_PU 0x55
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#define ADC5_GPIO5_100K_PU 0x56
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#define ADC5_GPIO6_100K_PU 0x57
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#define ADC5_GPIO7_100K_PU 0x58
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#define ADC5_SBUx_100K_PU 0x59
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/* 400k pull-up3 */
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#define ADC5_BAT_THERM_400K_PU 0x6a
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#define ADC5_BAT_ID_400K_PU 0x6b
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#define ADC5_XO_THERM_400K_PU 0x6c
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#define ADC5_AMUX_THM1_400K_PU 0x6d
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#define ADC5_AMUX_THM2_400K_PU 0x6e
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#define ADC5_AMUX_THM3_400K_PU 0x6f
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#define ADC5_AMUX_THM4_400K_PU 0x70
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#define ADC5_AMUX_THM5_400K_PU 0x71
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#define ADC5_GPIO1_400K_PU 0x72
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#define ADC5_GPIO2_400K_PU 0x73
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#define ADC5_GPIO3_400K_PU 0x74
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#define ADC5_GPIO4_400K_PU 0x75
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#define ADC5_GPIO5_400K_PU 0x76
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#define ADC5_GPIO6_400K_PU 0x77
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#define ADC5_GPIO7_400K_PU 0x78
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#define ADC5_SBUx_400K_PU 0x79
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/* 1/3 Divider */
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#define ADC5_GPIO1_DIV3 0x92
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#define ADC5_GPIO2_DIV3 0x93
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#define ADC5_GPIO3_DIV3 0x94
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#define ADC5_GPIO4_DIV3 0x95
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#define ADC5_GPIO5_DIV3 0x96
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#define ADC5_GPIO6_DIV3 0x97
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#define ADC5_GPIO7_DIV3 0x98
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#define ADC5_SBUx_DIV3 0x99
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/* Current and combined current/voltage channels */
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#define ADC5_INT_EXT_ISENSE 0xa1
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#define ADC5_PARALLEL_ISENSE 0xa5
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#define ADC5_CUR_REPLICA_VDS 0xa7
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#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9
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#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab
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#define ADC5_EXT_SENS_OFFSET 0xad
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#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0
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#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1
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#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2
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#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3
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#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4
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#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5
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#define ADC5_MAX_CHANNEL 0xc0
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/* ADC channels for ADC for PMIC7 */
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#define ADC7_REF_GND 0x00
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#define ADC7_1P25VREF 0x01
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#define ADC7_VREF_VADC 0x02
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#define ADC7_DIE_TEMP 0x03
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#define ADC7_AMUX_THM1 0x04
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#define ADC7_AMUX_THM2 0x05
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#define ADC7_AMUX_THM3 0x06
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#define ADC7_AMUX_THM4 0x07
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#define ADC7_AMUX_THM5 0x08
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#define ADC7_AMUX_THM6 0x09
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#define ADC7_GPIO1 0x0a
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#define ADC7_GPIO2 0x0b
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#define ADC7_GPIO3 0x0c
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#define ADC7_GPIO4 0x0d
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#define ADC7_CHG_TEMP 0x10
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#define ADC7_USB_IN_V_16 0x11
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#define ADC7_VDC_16 0x12
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#define ADC7_CC1_ID 0x13
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#define ADC7_VREF_BAT_THERM 0x15
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#define ADC7_IIN_FB 0x17
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/* 30k pull-up1 */
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#define ADC7_AMUX_THM1_30K_PU 0x24
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#define ADC7_AMUX_THM2_30K_PU 0x25
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#define ADC7_AMUX_THM3_30K_PU 0x26
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#define ADC7_AMUX_THM4_30K_PU 0x27
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#define ADC7_AMUX_THM5_30K_PU 0x28
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#define ADC7_AMUX_THM6_30K_PU 0x29
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#define ADC7_GPIO1_30K_PU 0x2a
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#define ADC7_GPIO2_30K_PU 0x2b
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#define ADC7_GPIO3_30K_PU 0x2c
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#define ADC7_GPIO4_30K_PU 0x2d
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#define ADC7_CC1_ID_30K_PU 0x33
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/* 100k pull-up2 */
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#define ADC7_AMUX_THM1_100K_PU 0x44
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#define ADC7_AMUX_THM2_100K_PU 0x45
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#define ADC7_AMUX_THM3_100K_PU 0x46
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#define ADC7_AMUX_THM4_100K_PU 0x47
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#define ADC7_AMUX_THM5_100K_PU 0x48
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#define ADC7_AMUX_THM6_100K_PU 0x49
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#define ADC7_GPIO1_100K_PU 0x4a
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#define ADC7_GPIO2_100K_PU 0x4b
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#define ADC7_GPIO3_100K_PU 0x4c
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#define ADC7_GPIO4_100K_PU 0x4d
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#define ADC7_CC1_ID_100K_PU 0x53
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/* 400k pull-up3 */
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#define ADC7_AMUX_THM1_400K_PU 0x64
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#define ADC7_AMUX_THM2_400K_PU 0x65
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#define ADC7_AMUX_THM3_400K_PU 0x66
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#define ADC7_AMUX_THM4_400K_PU 0x67
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#define ADC7_AMUX_THM5_400K_PU 0x68
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#define ADC7_AMUX_THM6_400K_PU 0x69
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#define ADC7_GPIO1_400K_PU 0x6a
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#define ADC7_GPIO2_400K_PU 0x6b
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#define ADC7_GPIO3_400K_PU 0x6c
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#define ADC7_GPIO4_400K_PU 0x6d
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#define ADC7_CC1_ID_400K_PU 0x73
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/* 1/3 Divider */
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#define ADC7_GPIO1_DIV3 0x8a
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#define ADC7_GPIO2_DIV3 0x8b
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#define ADC7_GPIO3_DIV3 0x8c
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#define ADC7_GPIO4_DIV3 0x8d
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#define ADC7_VPH_PWR 0x8e
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#define ADC7_VBAT_SNS 0x8f
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#define ADC7_SBUx 0x94
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#define ADC7_VBAT_2S_MID 0x96
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#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
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