forked from luck/tmp_suning_uos_patched
088e88be5a
Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs. The IP block contains settings for the PHY and a PLL. The PLL mode is configurable through a dedicated #phy-cell in .dts. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
12 lines
373 B
C
12 lines
373 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
|
*/
|
|
|
|
#define LANTIQ_PCIE_PHY_MODE_25MHZ 0
|
|
#define LANTIQ_PCIE_PHY_MODE_25MHZ_SSC 1
|
|
#define LANTIQ_PCIE_PHY_MODE_36MHZ 2
|
|
#define LANTIQ_PCIE_PHY_MODE_36MHZ_SSC 3
|
|
#define LANTIQ_PCIE_PHY_MODE_100MHZ 4
|
|
#define LANTIQ_PCIE_PHY_MODE_100MHZ_SSC 5
|