forked from luck/tmp_suning_uos_patched
51198ea947
The tpmi control registers can be accessed on the internal bus via an address with PCI attributes or IOP attributes (i.e. read-only, read-write... etc). The sas driver needs access to the iop-attribute registers for initialization. Changelog: * use ARRAY_SIZE for num_resources, Russell King Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
257 lines
7.0 KiB
C
257 lines
7.0 KiB
C
/*
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* iop13xx tpmi device resources
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* Copyright (c) 2005-2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/sizes.h>
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/* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */
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#define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12))
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#define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13))
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#define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10))
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#define IOP13XX_TPMI_IOP_CTRL(dev) (IOP13XX_TPMI_CTRL(dev) + 0x2000)
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#define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1)
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#define IOP13XX_TPMI_MEM_SIZE (255)
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#define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1)
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#define IOP13XX_TPMI_RESOURCE_MMR 0
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#define IOP13XX_TPMI_RESOURCE_MEM 1
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#define IOP13XX_TPMI_RESOURCE_CTRL 2
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#define IOP13XX_TPMI_RESOURCE_IOP_CTRL 3
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#define IOP13XX_TPMI_RESOURCE_IRQ 4
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static struct resource iop13xx_tpmi_0_resources[] = {
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[IOP13XX_TPMI_RESOURCE_MMR] = {
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.start = IOP13XX_TPMI_MMR(4), /* tpmi0 starts at dev == 4 */
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.end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_MEM] = {
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.start = IOP13XX_TPMI_MEM(0),
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.end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_CTRL] = {
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.start = IOP13XX_TPMI_CTRL(0),
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.end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
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.start = IOP13XX_TPMI_IOP_CTRL(0),
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.end = IOP13XX_TPMI_IOP_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_IRQ] = {
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.start = IRQ_IOP13XX_TPMI0_OUT,
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.end = IRQ_IOP13XX_TPMI0_OUT,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct resource iop13xx_tpmi_1_resources[] = {
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[IOP13XX_TPMI_RESOURCE_MMR] = {
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.start = IOP13XX_TPMI_MMR(1),
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.end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_MEM] = {
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.start = IOP13XX_TPMI_MEM(1),
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.end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_CTRL] = {
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.start = IOP13XX_TPMI_CTRL(1),
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.end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
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.start = IOP13XX_TPMI_IOP_CTRL(1),
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.end = IOP13XX_TPMI_IOP_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_IRQ] = {
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.start = IRQ_IOP13XX_TPMI1_OUT,
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.end = IRQ_IOP13XX_TPMI1_OUT,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct resource iop13xx_tpmi_2_resources[] = {
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[IOP13XX_TPMI_RESOURCE_MMR] = {
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.start = IOP13XX_TPMI_MMR(2),
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.end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_MEM] = {
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.start = IOP13XX_TPMI_MEM(2),
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.end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_CTRL] = {
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.start = IOP13XX_TPMI_CTRL(2),
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.end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
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.start = IOP13XX_TPMI_IOP_CTRL(2),
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.end = IOP13XX_TPMI_IOP_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_IRQ] = {
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.start = IRQ_IOP13XX_TPMI2_OUT,
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.end = IRQ_IOP13XX_TPMI2_OUT,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct resource iop13xx_tpmi_3_resources[] = {
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[IOP13XX_TPMI_RESOURCE_MMR] = {
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.start = IOP13XX_TPMI_MMR(3),
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.end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_MEM] = {
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.start = IOP13XX_TPMI_MEM(3),
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.end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_CTRL] = {
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.start = IOP13XX_TPMI_CTRL(3),
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.end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
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.start = IOP13XX_TPMI_IOP_CTRL(3),
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.end = IOP13XX_TPMI_IOP_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
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.flags = IORESOURCE_MEM,
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},
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[IOP13XX_TPMI_RESOURCE_IRQ] = {
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.start = IRQ_IOP13XX_TPMI3_OUT,
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.end = IRQ_IOP13XX_TPMI3_OUT,
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.flags = IORESOURCE_IRQ
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}
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};
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u64 iop13xx_tpmi_mask = DMA_64BIT_MASK;
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static struct platform_device iop13xx_tpmi_0_device = {
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.name = "iop-tpmi",
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.id = 0,
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.num_resources = ARRAY_SIZE(iop13xx_tpmi_0_resources),
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.resource = iop13xx_tpmi_0_resources,
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.dev = {
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.dma_mask = &iop13xx_tpmi_mask,
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.coherent_dma_mask = DMA_64BIT_MASK,
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},
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};
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static struct platform_device iop13xx_tpmi_1_device = {
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.name = "iop-tpmi",
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.id = 1,
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.num_resources = ARRAY_SIZE(iop13xx_tpmi_1_resources),
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.resource = iop13xx_tpmi_1_resources,
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.dev = {
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.dma_mask = &iop13xx_tpmi_mask,
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.coherent_dma_mask = DMA_64BIT_MASK,
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},
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};
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static struct platform_device iop13xx_tpmi_2_device = {
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.name = "iop-tpmi",
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.id = 2,
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.num_resources = ARRAY_SIZE(iop13xx_tpmi_2_resources),
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.resource = iop13xx_tpmi_2_resources,
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.dev = {
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.dma_mask = &iop13xx_tpmi_mask,
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.coherent_dma_mask = DMA_64BIT_MASK,
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},
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};
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static struct platform_device iop13xx_tpmi_3_device = {
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.name = "iop-tpmi",
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.id = 3,
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.num_resources = ARRAY_SIZE(iop13xx_tpmi_3_resources),
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.resource = iop13xx_tpmi_3_resources,
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.dev = {
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.dma_mask = &iop13xx_tpmi_mask,
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.coherent_dma_mask = DMA_64BIT_MASK,
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},
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};
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__init void iop13xx_add_tpmi_devices(void)
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{
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unsigned short device_id;
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/* tpmi's not present on iop341 or iop342 */
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if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
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/* ATUE must be present */
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device_id = __raw_readw(IOP13XX_ATUE_DID);
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else
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/* ATUX must be present */
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device_id = __raw_readw(IOP13XX_ATUX_DID);
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switch (device_id) {
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/* iop34[1|2] 0-tpmi */
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case 0x3380:
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case 0x3384:
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case 0x3388:
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case 0x338c:
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case 0x3382:
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case 0x3386:
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case 0x338a:
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case 0x338e:
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return;
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/* iop348 1-tpmi */
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case 0x3310:
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case 0x3312:
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case 0x3314:
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case 0x3318:
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case 0x331a:
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case 0x331c:
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case 0x33c0:
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case 0x33c2:
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case 0x33c4:
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case 0x33c8:
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case 0x33ca:
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case 0x33cc:
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case 0x33b0:
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case 0x33b2:
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case 0x33b4:
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case 0x33b8:
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case 0x33ba:
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case 0x33bc:
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case 0x3320:
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case 0x3322:
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case 0x3324:
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case 0x3328:
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case 0x332a:
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case 0x332c:
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platform_device_register(&iop13xx_tpmi_0_device);
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return;
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default:
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platform_device_register(&iop13xx_tpmi_0_device);
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platform_device_register(&iop13xx_tpmi_1_device);
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platform_device_register(&iop13xx_tpmi_2_device);
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platform_device_register(&iop13xx_tpmi_3_device);
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return;
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}
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}
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