forked from luck/tmp_suning_uos_patched
92704a1c63
On uniprocessor, it's always zero for optimize that. On SMP, the jmpl to the stub kills the return address stack in the cpu branch prediction logic, so expand the code sequence inline and use a code patching section to fix things up. This also always better and explicit register selection, which will be taken advantage of in a future changeset. The hard_smp_processor_id() function is big, so do not inline it. Fix up tests for Jalapeno to also test for Serrano chips too. These tests want "jbus Ultra-IIIi" cases to match, so that is what we should test for. Signed-off-by: David S. Miller <davem@davemloft.net>
1195 lines
28 KiB
C
1195 lines
28 KiB
C
/* smp.c: Sparc64 SMP support.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/pagemap.h>
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#include <linux/threads.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/fs.h>
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#include <linux/seq_file.h>
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#include <linux/cache.h>
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#include <linux/jiffies.h>
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#include <linux/profile.h>
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#include <linux/bootmem.h>
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#include <asm/head.h>
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#include <asm/ptrace.h>
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#include <asm/atomic.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#include <asm/cpudata.h>
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#include <asm/irq.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/oplib.h>
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#include <asm/uaccess.h>
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#include <asm/timer.h>
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#include <asm/starfire.h>
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#include <asm/tlb.h>
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#include <asm/sections.h>
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extern void calibrate_delay(void);
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/* Please don't make this stuff initdata!!! --DaveM */
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static unsigned char boot_cpu_id;
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cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
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cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
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static cpumask_t smp_commenced_mask;
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static cpumask_t cpu_callout_map;
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void smp_info(struct seq_file *m)
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{
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int i;
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seq_printf(m, "State:\n");
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for (i = 0; i < NR_CPUS; i++) {
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if (cpu_online(i))
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seq_printf(m,
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"CPU%d:\t\tonline\n", i);
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}
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}
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void smp_bogo(struct seq_file *m)
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{
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int i;
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for (i = 0; i < NR_CPUS; i++)
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if (cpu_online(i))
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seq_printf(m,
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"Cpu%dBogo\t: %lu.%02lu\n"
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"Cpu%dClkTck\t: %016lx\n",
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i, cpu_data(i).udelay_val / (500000/HZ),
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(cpu_data(i).udelay_val / (5000/HZ)) % 100,
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i, cpu_data(i).clock_tick);
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}
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void __init smp_store_cpu_info(int id)
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{
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int cpu_node;
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/* multiplier and counter set by
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smp_setup_percpu_timer() */
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cpu_data(id).udelay_val = loops_per_jiffy;
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cpu_find_by_mid(id, &cpu_node);
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cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
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"clock-frequency", 0);
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cpu_data(id).idle_volume = 1;
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cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
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16 * 1024);
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cpu_data(id).dcache_line_size =
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prom_getintdefault(cpu_node, "dcache-line-size", 32);
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cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
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16 * 1024);
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cpu_data(id).icache_line_size =
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prom_getintdefault(cpu_node, "icache-line-size", 32);
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cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
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4 * 1024 * 1024);
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cpu_data(id).ecache_line_size =
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prom_getintdefault(cpu_node, "ecache-line-size", 64);
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printk("CPU[%d]: Caches "
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"D[sz(%d):line_sz(%d)] "
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"I[sz(%d):line_sz(%d)] "
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"E[sz(%d):line_sz(%d)]\n",
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id,
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cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
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cpu_data(id).icache_size, cpu_data(id).icache_line_size,
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cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
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}
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static void smp_setup_percpu_timer(void);
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static volatile unsigned long callin_flag = 0;
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void __init smp_callin(void)
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{
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int cpuid = hard_smp_processor_id();
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__local_per_cpu_offset = __per_cpu_offset(cpuid);
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__flush_tlb_all();
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smp_setup_percpu_timer();
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if (cheetah_pcache_forced_on)
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cheetah_enable_pcache();
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local_irq_enable();
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calibrate_delay();
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smp_store_cpu_info(cpuid);
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callin_flag = 1;
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__asm__ __volatile__("membar #Sync\n\t"
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"flush %%g6" : : : "memory");
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/* Clear this or we will die instantly when we
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* schedule back to this idler...
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*/
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current_thread_info()->new_child = 0;
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/* Attach to the address space of init_task. */
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atomic_inc(&init_mm.mm_count);
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current->active_mm = &init_mm;
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while (!cpu_isset(cpuid, smp_commenced_mask))
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rmb();
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cpu_set(cpuid, cpu_online_map);
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/* idle thread is expected to have preempt disabled */
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preempt_disable();
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}
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void cpu_panic(void)
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{
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printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
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panic("SMP bolixed\n");
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}
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static unsigned long current_tick_offset __read_mostly;
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/* This tick register synchronization scheme is taken entirely from
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* the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
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*
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* The only change I've made is to rework it so that the master
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* initiates the synchonization instead of the slave. -DaveM
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*/
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#define MASTER 0
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#define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
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#define NUM_ROUNDS 64 /* magic value */
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#define NUM_ITERS 5 /* likewise */
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static DEFINE_SPINLOCK(itc_sync_lock);
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static unsigned long go[SLAVE + 1];
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#define DEBUG_TICK_SYNC 0
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static inline long get_delta (long *rt, long *master)
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{
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unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
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unsigned long tcenter, t0, t1, tm;
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unsigned long i;
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for (i = 0; i < NUM_ITERS; i++) {
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t0 = tick_ops->get_tick();
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go[MASTER] = 1;
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membar_storeload();
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while (!(tm = go[SLAVE]))
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rmb();
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go[SLAVE] = 0;
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wmb();
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t1 = tick_ops->get_tick();
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if (t1 - t0 < best_t1 - best_t0)
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best_t0 = t0, best_t1 = t1, best_tm = tm;
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}
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*rt = best_t1 - best_t0;
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*master = best_tm - best_t0;
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/* average best_t0 and best_t1 without overflow: */
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tcenter = (best_t0/2 + best_t1/2);
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if (best_t0 % 2 + best_t1 % 2 == 2)
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tcenter++;
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return tcenter - best_tm;
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}
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void smp_synchronize_tick_client(void)
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{
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long i, delta, adj, adjust_latency = 0, done = 0;
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unsigned long flags, rt, master_time_stamp, bound;
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#if DEBUG_TICK_SYNC
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struct {
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long rt; /* roundtrip time */
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long master; /* master's timestamp */
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long diff; /* difference between midpoint and master's timestamp */
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long lat; /* estimate of itc adjustment latency */
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} t[NUM_ROUNDS];
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#endif
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go[MASTER] = 1;
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while (go[MASTER])
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rmb();
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local_irq_save(flags);
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{
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for (i = 0; i < NUM_ROUNDS; i++) {
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delta = get_delta(&rt, &master_time_stamp);
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if (delta == 0) {
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done = 1; /* let's lock on to this... */
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bound = rt;
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}
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if (!done) {
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if (i > 0) {
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adjust_latency += -delta;
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adj = -delta + adjust_latency/4;
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} else
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adj = -delta;
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tick_ops->add_tick(adj, current_tick_offset);
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}
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#if DEBUG_TICK_SYNC
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t[i].rt = rt;
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t[i].master = master_time_stamp;
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t[i].diff = delta;
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t[i].lat = adjust_latency/4;
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#endif
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}
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}
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local_irq_restore(flags);
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#if DEBUG_TICK_SYNC
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for (i = 0; i < NUM_ROUNDS; i++)
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printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
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t[i].rt, t[i].master, t[i].diff, t[i].lat);
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#endif
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printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
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"maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
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}
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static void smp_start_sync_tick_client(int cpu);
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static void smp_synchronize_one_tick(int cpu)
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{
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unsigned long flags, i;
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go[MASTER] = 0;
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smp_start_sync_tick_client(cpu);
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/* wait for client to be ready */
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while (!go[MASTER])
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rmb();
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/* now let the client proceed into his loop */
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go[MASTER] = 0;
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membar_storeload();
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spin_lock_irqsave(&itc_sync_lock, flags);
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{
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for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
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while (!go[MASTER])
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rmb();
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go[MASTER] = 0;
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wmb();
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go[SLAVE] = tick_ops->get_tick();
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membar_storeload();
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}
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}
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spin_unlock_irqrestore(&itc_sync_lock, flags);
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}
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extern unsigned long sparc64_cpu_startup;
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/* The OBP cpu startup callback truncates the 3rd arg cookie to
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* 32-bits (I think) so to be safe we have it read the pointer
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* contained here so we work on >4GB machines. -DaveM
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*/
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static struct thread_info *cpu_new_thread = NULL;
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static int __devinit smp_boot_one_cpu(unsigned int cpu)
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{
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unsigned long entry =
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(unsigned long)(&sparc64_cpu_startup);
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unsigned long cookie =
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(unsigned long)(&cpu_new_thread);
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struct task_struct *p;
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int timeout, ret, cpu_node;
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p = fork_idle(cpu);
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callin_flag = 0;
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cpu_new_thread = task_thread_info(p);
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cpu_set(cpu, cpu_callout_map);
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cpu_find_by_mid(cpu, &cpu_node);
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prom_startcpu(cpu_node, entry, cookie);
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for (timeout = 0; timeout < 5000000; timeout++) {
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if (callin_flag)
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break;
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udelay(100);
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}
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if (callin_flag) {
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ret = 0;
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} else {
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printk("Processor %d is stuck.\n", cpu);
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cpu_clear(cpu, cpu_callout_map);
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ret = -ENODEV;
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}
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cpu_new_thread = NULL;
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return ret;
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}
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static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
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{
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u64 result, target;
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int stuck, tmp;
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if (this_is_starfire) {
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/* map to real upaid */
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cpu = (((cpu & 0x3c) << 1) |
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((cpu & 0x40) >> 4) |
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(cpu & 0x3));
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}
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target = (cpu << 14) | 0x70;
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again:
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/* Ok, this is the real Spitfire Errata #54.
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* One must read back from a UDB internal register
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* after writes to the UDB interrupt dispatch, but
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* before the membar Sync for that write.
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* So we use the high UDB control register (ASI 0x7f,
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* ADDR 0x20) for the dummy read. -DaveM
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*/
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tmp = 0x40;
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__asm__ __volatile__(
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"wrpr %1, %2, %%pstate\n\t"
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"stxa %4, [%0] %3\n\t"
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"stxa %5, [%0+%8] %3\n\t"
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"add %0, %8, %0\n\t"
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"stxa %6, [%0+%8] %3\n\t"
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"membar #Sync\n\t"
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"stxa %%g0, [%7] %3\n\t"
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"membar #Sync\n\t"
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"mov 0x20, %%g1\n\t"
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"ldxa [%%g1] 0x7f, %%g0\n\t"
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"membar #Sync"
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: "=r" (tmp)
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: "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
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"r" (data0), "r" (data1), "r" (data2), "r" (target),
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"r" (0x10), "0" (tmp)
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: "g1");
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/* NOTE: PSTATE_IE is still clear. */
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stuck = 100000;
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do {
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__asm__ __volatile__("ldxa [%%g0] %1, %0"
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: "=r" (result)
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: "i" (ASI_INTR_DISPATCH_STAT));
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if (result == 0) {
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__asm__ __volatile__("wrpr %0, 0x0, %%pstate"
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: : "r" (pstate));
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return;
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}
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stuck -= 1;
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if (stuck == 0)
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break;
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} while (result & 0x1);
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__asm__ __volatile__("wrpr %0, 0x0, %%pstate"
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: : "r" (pstate));
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if (stuck == 0) {
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printk("CPU[%d]: mondo stuckage result[%016lx]\n",
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smp_processor_id(), result);
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} else {
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udelay(2);
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goto again;
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}
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}
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static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
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{
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u64 pstate;
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int i;
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__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
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for_each_cpu_mask(i, mask)
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spitfire_xcall_helper(data0, data1, data2, pstate, i);
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}
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/* Cheetah now allows to send the whole 64-bytes of data in the interrupt
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* packet, but we have no use for that. However we do take advantage of
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* the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
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*/
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static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
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{
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u64 pstate, ver;
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int nack_busy_id, is_jbus;
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if (cpus_empty(mask))
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return;
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/* Unfortunately, someone at Sun had the brilliant idea to make the
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* busy/nack fields hard-coded by ITID number for this Ultra-III
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* derivative processor.
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*/
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__asm__ ("rdpr %%ver, %0" : "=r" (ver));
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is_jbus = ((ver >> 32) == __JALAPENO_ID ||
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(ver >> 32) == __SERRANO_ID);
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__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
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retry:
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__asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
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: : "r" (pstate), "i" (PSTATE_IE));
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/* Setup the dispatch data registers. */
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__asm__ __volatile__("stxa %0, [%3] %6\n\t"
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"stxa %1, [%4] %6\n\t"
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"stxa %2, [%5] %6\n\t"
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"membar #Sync\n\t"
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: /* no outputs */
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: "r" (data0), "r" (data1), "r" (data2),
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"r" (0x40), "r" (0x50), "r" (0x60),
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"i" (ASI_INTR_W));
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nack_busy_id = 0;
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{
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int i;
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for_each_cpu_mask(i, mask) {
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u64 target = (i << 14) | 0x70;
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if (!is_jbus)
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target |= (nack_busy_id << 24);
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__asm__ __volatile__(
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"stxa %%g0, [%0] %1\n\t"
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"membar #Sync\n\t"
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: /* no outputs */
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: "r" (target), "i" (ASI_INTR_W));
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nack_busy_id++;
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}
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}
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/* Now, poll for completion. */
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{
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u64 dispatch_stat;
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long stuck;
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stuck = 100000 * nack_busy_id;
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do {
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__asm__ __volatile__("ldxa [%%g0] %1, %0"
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: "=r" (dispatch_stat)
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: "i" (ASI_INTR_DISPATCH_STAT));
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if (dispatch_stat == 0UL) {
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__asm__ __volatile__("wrpr %0, 0x0, %%pstate"
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: : "r" (pstate));
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return;
|
|
}
|
|
if (!--stuck)
|
|
break;
|
|
} while (dispatch_stat & 0x5555555555555555UL);
|
|
|
|
__asm__ __volatile__("wrpr %0, 0x0, %%pstate"
|
|
: : "r" (pstate));
|
|
|
|
if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
|
|
/* Busy bits will not clear, continue instead
|
|
* of freezing up on this cpu.
|
|
*/
|
|
printk("CPU[%d]: mondo stuckage result[%016lx]\n",
|
|
smp_processor_id(), dispatch_stat);
|
|
} else {
|
|
int i, this_busy_nack = 0;
|
|
|
|
/* Delay some random time with interrupts enabled
|
|
* to prevent deadlock.
|
|
*/
|
|
udelay(2 * nack_busy_id);
|
|
|
|
/* Clear out the mask bits for cpus which did not
|
|
* NACK us.
|
|
*/
|
|
for_each_cpu_mask(i, mask) {
|
|
u64 check_mask;
|
|
|
|
if (is_jbus)
|
|
check_mask = (0x2UL << (2*i));
|
|
else
|
|
check_mask = (0x2UL <<
|
|
this_busy_nack);
|
|
if ((dispatch_stat & check_mask) == 0)
|
|
cpu_clear(i, mask);
|
|
this_busy_nack += 2;
|
|
}
|
|
|
|
goto retry;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Send cross call to all processors mentioned in MASK
|
|
* except self.
|
|
*/
|
|
static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
|
|
{
|
|
u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
|
|
int this_cpu = get_cpu();
|
|
|
|
cpus_and(mask, mask, cpu_online_map);
|
|
cpu_clear(this_cpu, mask);
|
|
|
|
if (tlb_type == spitfire)
|
|
spitfire_xcall_deliver(data0, data1, data2, mask);
|
|
else
|
|
cheetah_xcall_deliver(data0, data1, data2, mask);
|
|
/* NOTE: Caller runs local copy on master. */
|
|
|
|
put_cpu();
|
|
}
|
|
|
|
extern unsigned long xcall_sync_tick;
|
|
|
|
static void smp_start_sync_tick_client(int cpu)
|
|
{
|
|
cpumask_t mask = cpumask_of_cpu(cpu);
|
|
|
|
smp_cross_call_masked(&xcall_sync_tick,
|
|
0, 0, 0, mask);
|
|
}
|
|
|
|
/* Send cross call to all processors except self. */
|
|
#define smp_cross_call(func, ctx, data1, data2) \
|
|
smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
|
|
|
|
struct call_data_struct {
|
|
void (*func) (void *info);
|
|
void *info;
|
|
atomic_t finished;
|
|
int wait;
|
|
};
|
|
|
|
static DEFINE_SPINLOCK(call_lock);
|
|
static struct call_data_struct *call_data;
|
|
|
|
extern unsigned long xcall_call_function;
|
|
|
|
/*
|
|
* You must not call this function with disabled interrupts or from a
|
|
* hardware interrupt handler or from a bottom half handler.
|
|
*/
|
|
static int smp_call_function_mask(void (*func)(void *info), void *info,
|
|
int nonatomic, int wait, cpumask_t mask)
|
|
{
|
|
struct call_data_struct data;
|
|
int cpus = cpus_weight(mask) - 1;
|
|
long timeout;
|
|
|
|
if (!cpus)
|
|
return 0;
|
|
|
|
/* Can deadlock when called with interrupts disabled */
|
|
WARN_ON(irqs_disabled());
|
|
|
|
data.func = func;
|
|
data.info = info;
|
|
atomic_set(&data.finished, 0);
|
|
data.wait = wait;
|
|
|
|
spin_lock(&call_lock);
|
|
|
|
call_data = &data;
|
|
|
|
smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
|
|
|
|
/*
|
|
* Wait for other cpus to complete function or at
|
|
* least snap the call data.
|
|
*/
|
|
timeout = 1000000;
|
|
while (atomic_read(&data.finished) != cpus) {
|
|
if (--timeout <= 0)
|
|
goto out_timeout;
|
|
barrier();
|
|
udelay(1);
|
|
}
|
|
|
|
spin_unlock(&call_lock);
|
|
|
|
return 0;
|
|
|
|
out_timeout:
|
|
spin_unlock(&call_lock);
|
|
printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
|
|
(long) num_online_cpus() - 1L,
|
|
(long) atomic_read(&data.finished));
|
|
return 0;
|
|
}
|
|
|
|
int smp_call_function(void (*func)(void *info), void *info,
|
|
int nonatomic, int wait)
|
|
{
|
|
return smp_call_function_mask(func, info, nonatomic, wait,
|
|
cpu_online_map);
|
|
}
|
|
|
|
void smp_call_function_client(int irq, struct pt_regs *regs)
|
|
{
|
|
void (*func) (void *info) = call_data->func;
|
|
void *info = call_data->info;
|
|
|
|
clear_softint(1 << irq);
|
|
if (call_data->wait) {
|
|
/* let initiator proceed only after completion */
|
|
func(info);
|
|
atomic_inc(&call_data->finished);
|
|
} else {
|
|
/* let initiator proceed after getting data */
|
|
atomic_inc(&call_data->finished);
|
|
func(info);
|
|
}
|
|
}
|
|
|
|
static void tsb_sync(void *info)
|
|
{
|
|
struct mm_struct *mm = info;
|
|
|
|
if (current->active_mm == mm)
|
|
tsb_context_switch(mm);
|
|
}
|
|
|
|
void smp_tsb_sync(struct mm_struct *mm)
|
|
{
|
|
smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
|
|
}
|
|
|
|
extern unsigned long xcall_flush_tlb_mm;
|
|
extern unsigned long xcall_flush_tlb_pending;
|
|
extern unsigned long xcall_flush_tlb_kernel_range;
|
|
extern unsigned long xcall_report_regs;
|
|
extern unsigned long xcall_receive_signal;
|
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
extern unsigned long xcall_flush_dcache_page_cheetah;
|
|
#endif
|
|
extern unsigned long xcall_flush_dcache_page_spitfire;
|
|
|
|
#ifdef CONFIG_DEBUG_DCFLUSH
|
|
extern atomic_t dcpage_flushes;
|
|
extern atomic_t dcpage_flushes_xcall;
|
|
#endif
|
|
|
|
static __inline__ void __local_flush_dcache_page(struct page *page)
|
|
{
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
__flush_dcache_page(page_address(page),
|
|
((tlb_type == spitfire) &&
|
|
page_mapping(page) != NULL));
|
|
#else
|
|
if (page_mapping(page) != NULL &&
|
|
tlb_type == spitfire)
|
|
__flush_icache_page(__pa(page_address(page)));
|
|
#endif
|
|
}
|
|
|
|
void smp_flush_dcache_page_impl(struct page *page, int cpu)
|
|
{
|
|
cpumask_t mask = cpumask_of_cpu(cpu);
|
|
int this_cpu = get_cpu();
|
|
|
|
#ifdef CONFIG_DEBUG_DCFLUSH
|
|
atomic_inc(&dcpage_flushes);
|
|
#endif
|
|
if (cpu == this_cpu) {
|
|
__local_flush_dcache_page(page);
|
|
} else if (cpu_online(cpu)) {
|
|
void *pg_addr = page_address(page);
|
|
u64 data0;
|
|
|
|
if (tlb_type == spitfire) {
|
|
data0 =
|
|
((u64)&xcall_flush_dcache_page_spitfire);
|
|
if (page_mapping(page) != NULL)
|
|
data0 |= ((u64)1 << 32);
|
|
spitfire_xcall_deliver(data0,
|
|
__pa(pg_addr),
|
|
(u64) pg_addr,
|
|
mask);
|
|
} else {
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
data0 =
|
|
((u64)&xcall_flush_dcache_page_cheetah);
|
|
cheetah_xcall_deliver(data0,
|
|
__pa(pg_addr),
|
|
0, mask);
|
|
#endif
|
|
}
|
|
#ifdef CONFIG_DEBUG_DCFLUSH
|
|
atomic_inc(&dcpage_flushes_xcall);
|
|
#endif
|
|
}
|
|
|
|
put_cpu();
|
|
}
|
|
|
|
void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
|
|
{
|
|
void *pg_addr = page_address(page);
|
|
cpumask_t mask = cpu_online_map;
|
|
u64 data0;
|
|
int this_cpu = get_cpu();
|
|
|
|
cpu_clear(this_cpu, mask);
|
|
|
|
#ifdef CONFIG_DEBUG_DCFLUSH
|
|
atomic_inc(&dcpage_flushes);
|
|
#endif
|
|
if (cpus_empty(mask))
|
|
goto flush_self;
|
|
if (tlb_type == spitfire) {
|
|
data0 = ((u64)&xcall_flush_dcache_page_spitfire);
|
|
if (page_mapping(page) != NULL)
|
|
data0 |= ((u64)1 << 32);
|
|
spitfire_xcall_deliver(data0,
|
|
__pa(pg_addr),
|
|
(u64) pg_addr,
|
|
mask);
|
|
} else {
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
data0 = ((u64)&xcall_flush_dcache_page_cheetah);
|
|
cheetah_xcall_deliver(data0,
|
|
__pa(pg_addr),
|
|
0, mask);
|
|
#endif
|
|
}
|
|
#ifdef CONFIG_DEBUG_DCFLUSH
|
|
atomic_inc(&dcpage_flushes_xcall);
|
|
#endif
|
|
flush_self:
|
|
__local_flush_dcache_page(page);
|
|
|
|
put_cpu();
|
|
}
|
|
|
|
void smp_receive_signal(int cpu)
|
|
{
|
|
cpumask_t mask = cpumask_of_cpu(cpu);
|
|
|
|
if (cpu_online(cpu)) {
|
|
u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
|
|
|
|
if (tlb_type == spitfire)
|
|
spitfire_xcall_deliver(data0, 0, 0, mask);
|
|
else
|
|
cheetah_xcall_deliver(data0, 0, 0, mask);
|
|
}
|
|
}
|
|
|
|
void smp_receive_signal_client(int irq, struct pt_regs *regs)
|
|
{
|
|
/* Just return, rtrap takes care of the rest. */
|
|
clear_softint(1 << irq);
|
|
}
|
|
|
|
void smp_report_regs(void)
|
|
{
|
|
smp_cross_call(&xcall_report_regs, 0, 0, 0);
|
|
}
|
|
|
|
/* We know that the window frames of the user have been flushed
|
|
* to the stack before we get here because all callers of us
|
|
* are flush_tlb_*() routines, and these run after flush_cache_*()
|
|
* which performs the flushw.
|
|
*
|
|
* The SMP TLB coherency scheme we use works as follows:
|
|
*
|
|
* 1) mm->cpu_vm_mask is a bit mask of which cpus an address
|
|
* space has (potentially) executed on, this is the heuristic
|
|
* we use to avoid doing cross calls.
|
|
*
|
|
* Also, for flushing from kswapd and also for clones, we
|
|
* use cpu_vm_mask as the list of cpus to make run the TLB.
|
|
*
|
|
* 2) TLB context numbers are shared globally across all processors
|
|
* in the system, this allows us to play several games to avoid
|
|
* cross calls.
|
|
*
|
|
* One invariant is that when a cpu switches to a process, and
|
|
* that processes tsk->active_mm->cpu_vm_mask does not have the
|
|
* current cpu's bit set, that tlb context is flushed locally.
|
|
*
|
|
* If the address space is non-shared (ie. mm->count == 1) we avoid
|
|
* cross calls when we want to flush the currently running process's
|
|
* tlb state. This is done by clearing all cpu bits except the current
|
|
* processor's in current->active_mm->cpu_vm_mask and performing the
|
|
* flush locally only. This will force any subsequent cpus which run
|
|
* this task to flush the context from the local tlb if the process
|
|
* migrates to another cpu (again).
|
|
*
|
|
* 3) For shared address spaces (threads) and swapping we bite the
|
|
* bullet for most cases and perform the cross call (but only to
|
|
* the cpus listed in cpu_vm_mask).
|
|
*
|
|
* The performance gain from "optimizing" away the cross call for threads is
|
|
* questionable (in theory the big win for threads is the massive sharing of
|
|
* address space state across processors).
|
|
*/
|
|
|
|
/* This currently is only used by the hugetlb arch pre-fault
|
|
* hook on UltraSPARC-III+ and later when changing the pagesize
|
|
* bits of the context register for an address space.
|
|
*/
|
|
void smp_flush_tlb_mm(struct mm_struct *mm)
|
|
{
|
|
u32 ctx = CTX_HWBITS(mm->context);
|
|
int cpu = get_cpu();
|
|
|
|
if (atomic_read(&mm->mm_users) == 1) {
|
|
mm->cpu_vm_mask = cpumask_of_cpu(cpu);
|
|
goto local_flush_and_out;
|
|
}
|
|
|
|
smp_cross_call_masked(&xcall_flush_tlb_mm,
|
|
ctx, 0, 0,
|
|
mm->cpu_vm_mask);
|
|
|
|
local_flush_and_out:
|
|
__flush_tlb_mm(ctx, SECONDARY_CONTEXT);
|
|
|
|
put_cpu();
|
|
}
|
|
|
|
void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
|
|
{
|
|
u32 ctx = CTX_HWBITS(mm->context);
|
|
int cpu = get_cpu();
|
|
|
|
if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
|
|
mm->cpu_vm_mask = cpumask_of_cpu(cpu);
|
|
else
|
|
smp_cross_call_masked(&xcall_flush_tlb_pending,
|
|
ctx, nr, (unsigned long) vaddrs,
|
|
mm->cpu_vm_mask);
|
|
|
|
__flush_tlb_pending(ctx, nr, vaddrs);
|
|
|
|
put_cpu();
|
|
}
|
|
|
|
void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
|
|
{
|
|
start &= PAGE_MASK;
|
|
end = PAGE_ALIGN(end);
|
|
if (start != end) {
|
|
smp_cross_call(&xcall_flush_tlb_kernel_range,
|
|
0, start, end);
|
|
|
|
__flush_tlb_kernel_range(start, end);
|
|
}
|
|
}
|
|
|
|
/* CPU capture. */
|
|
/* #define CAPTURE_DEBUG */
|
|
extern unsigned long xcall_capture;
|
|
|
|
static atomic_t smp_capture_depth = ATOMIC_INIT(0);
|
|
static atomic_t smp_capture_registry = ATOMIC_INIT(0);
|
|
static unsigned long penguins_are_doing_time;
|
|
|
|
void smp_capture(void)
|
|
{
|
|
int result = atomic_add_ret(1, &smp_capture_depth);
|
|
|
|
if (result == 1) {
|
|
int ncpus = num_online_cpus();
|
|
|
|
#ifdef CAPTURE_DEBUG
|
|
printk("CPU[%d]: Sending penguins to jail...",
|
|
smp_processor_id());
|
|
#endif
|
|
penguins_are_doing_time = 1;
|
|
membar_storestore_loadstore();
|
|
atomic_inc(&smp_capture_registry);
|
|
smp_cross_call(&xcall_capture, 0, 0, 0);
|
|
while (atomic_read(&smp_capture_registry) != ncpus)
|
|
rmb();
|
|
#ifdef CAPTURE_DEBUG
|
|
printk("done\n");
|
|
#endif
|
|
}
|
|
}
|
|
|
|
void smp_release(void)
|
|
{
|
|
if (atomic_dec_and_test(&smp_capture_depth)) {
|
|
#ifdef CAPTURE_DEBUG
|
|
printk("CPU[%d]: Giving pardon to "
|
|
"imprisoned penguins\n",
|
|
smp_processor_id());
|
|
#endif
|
|
penguins_are_doing_time = 0;
|
|
membar_storeload_storestore();
|
|
atomic_dec(&smp_capture_registry);
|
|
}
|
|
}
|
|
|
|
/* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
|
|
* can service tlb flush xcalls...
|
|
*/
|
|
extern void prom_world(int);
|
|
|
|
void smp_penguin_jailcell(int irq, struct pt_regs *regs)
|
|
{
|
|
clear_softint(1 << irq);
|
|
|
|
preempt_disable();
|
|
|
|
__asm__ __volatile__("flushw");
|
|
prom_world(1);
|
|
atomic_inc(&smp_capture_registry);
|
|
membar_storeload_storestore();
|
|
while (penguins_are_doing_time)
|
|
rmb();
|
|
atomic_dec(&smp_capture_registry);
|
|
prom_world(0);
|
|
|
|
preempt_enable();
|
|
}
|
|
|
|
#define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
|
|
#define prof_counter(__cpu) cpu_data(__cpu).counter
|
|
|
|
void smp_percpu_timer_interrupt(struct pt_regs *regs)
|
|
{
|
|
unsigned long compare, tick, pstate;
|
|
int cpu = smp_processor_id();
|
|
int user = user_mode(regs);
|
|
|
|
/*
|
|
* Check for level 14 softint.
|
|
*/
|
|
{
|
|
unsigned long tick_mask = tick_ops->softint_mask;
|
|
|
|
if (!(get_softint() & tick_mask)) {
|
|
extern void handler_irq(int, struct pt_regs *);
|
|
|
|
handler_irq(14, regs);
|
|
return;
|
|
}
|
|
clear_softint(tick_mask);
|
|
}
|
|
|
|
do {
|
|
profile_tick(CPU_PROFILING, regs);
|
|
if (!--prof_counter(cpu)) {
|
|
irq_enter();
|
|
|
|
if (cpu == boot_cpu_id) {
|
|
kstat_this_cpu.irqs[0]++;
|
|
timer_tick_interrupt(regs);
|
|
}
|
|
|
|
update_process_times(user);
|
|
|
|
irq_exit();
|
|
|
|
prof_counter(cpu) = prof_multiplier(cpu);
|
|
}
|
|
|
|
/* Guarantee that the following sequences execute
|
|
* uninterrupted.
|
|
*/
|
|
__asm__ __volatile__("rdpr %%pstate, %0\n\t"
|
|
"wrpr %0, %1, %%pstate"
|
|
: "=r" (pstate)
|
|
: "i" (PSTATE_IE));
|
|
|
|
compare = tick_ops->add_compare(current_tick_offset);
|
|
tick = tick_ops->get_tick();
|
|
|
|
/* Restore PSTATE_IE. */
|
|
__asm__ __volatile__("wrpr %0, 0x0, %%pstate"
|
|
: /* no outputs */
|
|
: "r" (pstate));
|
|
} while (time_after_eq(tick, compare));
|
|
}
|
|
|
|
static void __init smp_setup_percpu_timer(void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
unsigned long pstate;
|
|
|
|
prof_counter(cpu) = prof_multiplier(cpu) = 1;
|
|
|
|
/* Guarantee that the following sequences execute
|
|
* uninterrupted.
|
|
*/
|
|
__asm__ __volatile__("rdpr %%pstate, %0\n\t"
|
|
"wrpr %0, %1, %%pstate"
|
|
: "=r" (pstate)
|
|
: "i" (PSTATE_IE));
|
|
|
|
tick_ops->init_tick(current_tick_offset);
|
|
|
|
/* Restore PSTATE_IE. */
|
|
__asm__ __volatile__("wrpr %0, 0x0, %%pstate"
|
|
: /* no outputs */
|
|
: "r" (pstate));
|
|
}
|
|
|
|
void __init smp_tick_init(void)
|
|
{
|
|
boot_cpu_id = hard_smp_processor_id();
|
|
current_tick_offset = timer_tick_offset;
|
|
|
|
cpu_set(boot_cpu_id, cpu_online_map);
|
|
prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
|
|
}
|
|
|
|
/* /proc/profile writes can call this, don't __init it please. */
|
|
static DEFINE_SPINLOCK(prof_setup_lock);
|
|
|
|
int setup_profiling_timer(unsigned int multiplier)
|
|
{
|
|
unsigned long flags;
|
|
int i;
|
|
|
|
if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
|
|
return -EINVAL;
|
|
|
|
spin_lock_irqsave(&prof_setup_lock, flags);
|
|
for (i = 0; i < NR_CPUS; i++)
|
|
prof_multiplier(i) = multiplier;
|
|
current_tick_offset = (timer_tick_offset / multiplier);
|
|
spin_unlock_irqrestore(&prof_setup_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Constrain the number of cpus to max_cpus. */
|
|
void __init smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
if (num_possible_cpus() > max_cpus) {
|
|
int instance, mid;
|
|
|
|
instance = 0;
|
|
while (!cpu_find_by_instance(instance, NULL, &mid)) {
|
|
if (mid != boot_cpu_id) {
|
|
cpu_clear(mid, phys_cpu_present_map);
|
|
if (num_possible_cpus() <= max_cpus)
|
|
break;
|
|
}
|
|
instance++;
|
|
}
|
|
}
|
|
|
|
smp_store_cpu_info(boot_cpu_id);
|
|
}
|
|
|
|
/* Set this up early so that things like the scheduler can init
|
|
* properly. We use the same cpu mask for both the present and
|
|
* possible cpu map.
|
|
*/
|
|
void __init smp_setup_cpu_possible_map(void)
|
|
{
|
|
int instance, mid;
|
|
|
|
instance = 0;
|
|
while (!cpu_find_by_instance(instance, NULL, &mid)) {
|
|
if (mid < NR_CPUS)
|
|
cpu_set(mid, phys_cpu_present_map);
|
|
instance++;
|
|
}
|
|
}
|
|
|
|
void __devinit smp_prepare_boot_cpu(void)
|
|
{
|
|
int cpu = hard_smp_processor_id();
|
|
|
|
if (cpu >= NR_CPUS) {
|
|
prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
|
|
prom_halt();
|
|
}
|
|
|
|
current_thread_info()->cpu = cpu;
|
|
__local_per_cpu_offset = __per_cpu_offset(cpu);
|
|
|
|
cpu_set(smp_processor_id(), cpu_online_map);
|
|
cpu_set(smp_processor_id(), phys_cpu_present_map);
|
|
}
|
|
|
|
int __devinit __cpu_up(unsigned int cpu)
|
|
{
|
|
int ret = smp_boot_one_cpu(cpu);
|
|
|
|
if (!ret) {
|
|
cpu_set(cpu, smp_commenced_mask);
|
|
while (!cpu_isset(cpu, cpu_online_map))
|
|
mb();
|
|
if (!cpu_isset(cpu, cpu_online_map)) {
|
|
ret = -ENODEV;
|
|
} else {
|
|
smp_synchronize_one_tick(cpu);
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
void __init smp_cpus_done(unsigned int max_cpus)
|
|
{
|
|
unsigned long bogosum = 0;
|
|
int i;
|
|
|
|
for (i = 0; i < NR_CPUS; i++) {
|
|
if (cpu_online(i))
|
|
bogosum += cpu_data(i).udelay_val;
|
|
}
|
|
printk("Total of %ld processors activated "
|
|
"(%lu.%02lu BogoMIPS).\n",
|
|
(long) num_online_cpus(),
|
|
bogosum/(500000/HZ),
|
|
(bogosum/(5000/HZ))%100);
|
|
}
|
|
|
|
void smp_send_reschedule(int cpu)
|
|
{
|
|
smp_receive_signal(cpu);
|
|
}
|
|
|
|
/* This is a nop because we capture all other cpus
|
|
* anyways when making the PROM active.
|
|
*/
|
|
void smp_send_stop(void)
|
|
{
|
|
}
|
|
|
|
unsigned long __per_cpu_base __read_mostly;
|
|
unsigned long __per_cpu_shift __read_mostly;
|
|
|
|
EXPORT_SYMBOL(__per_cpu_base);
|
|
EXPORT_SYMBOL(__per_cpu_shift);
|
|
|
|
void __init setup_per_cpu_areas(void)
|
|
{
|
|
unsigned long goal, size, i;
|
|
char *ptr;
|
|
|
|
/* Copy section for each CPU (we discard the original) */
|
|
goal = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES);
|
|
#ifdef CONFIG_MODULES
|
|
if (goal < PERCPU_ENOUGH_ROOM)
|
|
goal = PERCPU_ENOUGH_ROOM;
|
|
#endif
|
|
__per_cpu_shift = 0;
|
|
for (size = 1UL; size < goal; size <<= 1UL)
|
|
__per_cpu_shift++;
|
|
|
|
ptr = alloc_bootmem(size * NR_CPUS);
|
|
|
|
__per_cpu_base = ptr - __per_cpu_start;
|
|
|
|
for (i = 0; i < NR_CPUS; i++, ptr += size)
|
|
memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
|
|
}
|