forked from luck/tmp_suning_uos_patched
bbc9e2f452
The mapping between cpu/apicid and node is done via apicid_to_node[] on 64bit and apicid_2_node[] + apic->x86_32_numa_cpu_node() on 32bit. This difference makes it difficult to further unify 32 and 64bit NUMA handling. This patch unifies it by replacing both apicid_to_node[] and apicid_2_node[] with __apicid_to_node[] array, which is accessed by two accessors - set_apicid_to_node() and numa_cpu_node(). On 64bit, numa_cpu_node() always consults __apicid_to_node[] directly while 32bit goes through apic->numa_cpu_node() method to allow apic implementations to override it. srat_detect_node() for amd cpus contains workaround for broken NUMA configuration which assumes relationship between APIC ID, HT node ID and NUMA topology. Leave it to access __apicid_to_node[] directly as mapping through CPU might result in undesirable behavior change. The comment is reformatted and updated to note the ugliness. Signed-off-by: Tejun Heo <tj@kernel.org> Reviewed-by: Pekka Enberg <penberg@kernel.org> Cc: eric.dumazet@gmail.com Cc: yinghai@kernel.org Cc: brgerst@gmail.com Cc: gorcunov@gmail.com Cc: shaohui.zheng@intel.com Cc: rientjes@google.com LKML-Reference: <1295789862-25482-14-git-send-email-tj@kernel.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Cc: David Rientjes <rientjes@google.com>
176 lines
4.6 KiB
C
176 lines
4.6 KiB
C
#ifndef _ASM_X86_MPSPEC_H
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#define _ASM_X86_MPSPEC_H
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#include <linux/init.h>
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#include <asm/mpspec_def.h>
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#include <asm/x86_init.h>
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#include <asm/apicdef.h>
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extern int apic_version[];
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extern int pic_mode;
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#ifdef CONFIG_X86_32
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/*
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* Summit or generic (i.e. installer) kernels need lots of bus entries.
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* Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets.
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*/
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#if CONFIG_BASE_SMALL == 0
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# define MAX_MP_BUSSES 260
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#else
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# define MAX_MP_BUSSES 32
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#endif
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#define MAX_IRQ_SOURCES 256
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extern unsigned int def_to_bigsmp;
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#ifdef CONFIG_X86_NUMAQ
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extern int mp_bus_id_to_node[MAX_MP_BUSSES];
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extern int mp_bus_id_to_local[MAX_MP_BUSSES];
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extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
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#endif
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#else /* CONFIG_X86_64: */
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#define MAX_MP_BUSSES 256
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/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
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#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
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#endif /* CONFIG_X86_64 */
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#if defined(CONFIG_MCA) || defined(CONFIG_EISA)
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extern int mp_bus_id_to_type[MAX_MP_BUSSES];
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#endif
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extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
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extern unsigned int boot_cpu_physical_apicid;
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extern unsigned int max_physical_apicid;
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extern int mpc_default_type;
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extern unsigned long mp_lapic_addr;
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#ifdef CONFIG_X86_LOCAL_APIC
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extern int smp_found_config;
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#else
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# define smp_found_config 0
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#endif
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static inline void get_smp_config(void)
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{
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x86_init.mpparse.get_smp_config(0);
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}
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static inline void early_get_smp_config(void)
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{
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x86_init.mpparse.get_smp_config(1);
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}
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static inline void find_smp_config(void)
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{
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x86_init.mpparse.find_smp_config();
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}
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#ifdef CONFIG_X86_MPPARSE
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extern void early_reserve_e820_mpc_new(void);
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extern int enable_update_mptable;
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extern int default_mpc_apic_id(struct mpc_cpu *m);
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extern void default_smp_read_mpc_oem(struct mpc_table *mpc);
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# ifdef CONFIG_X86_IO_APIC
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extern void default_mpc_oem_bus_info(struct mpc_bus *m, char *str);
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# else
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# define default_mpc_oem_bus_info NULL
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# endif
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extern void default_find_smp_config(void);
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extern void default_get_smp_config(unsigned int early);
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#else
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static inline void early_reserve_e820_mpc_new(void) { }
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#define enable_update_mptable 0
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#define default_mpc_apic_id NULL
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#define default_smp_read_mpc_oem NULL
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#define default_mpc_oem_bus_info NULL
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#define default_find_smp_config x86_init_noop
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#define default_get_smp_config x86_init_uint_noop
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#endif
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void __cpuinit generic_processor_info(int apicid, int version);
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#ifdef CONFIG_ACPI
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extern void mp_register_ioapic(int id, u32 address, u32 gsi_base);
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extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
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u32 gsi);
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extern void mp_config_acpi_legacy_irqs(void);
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struct device;
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extern int mp_register_gsi(struct device *dev, u32 gsi, int edge_level,
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int active_high_low);
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#endif /* CONFIG_ACPI */
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#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC)
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struct physid_mask {
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unsigned long mask[PHYSID_ARRAY_SIZE];
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};
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typedef struct physid_mask physid_mask_t;
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#define physid_set(physid, map) set_bit(physid, (map).mask)
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#define physid_clear(physid, map) clear_bit(physid, (map).mask)
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#define physid_isset(physid, map) test_bit(physid, (map).mask)
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#define physid_test_and_set(physid, map) \
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test_and_set_bit(physid, (map).mask)
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#define physids_and(dst, src1, src2) \
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bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
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#define physids_or(dst, src1, src2) \
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bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
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#define physids_clear(map) \
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bitmap_zero((map).mask, MAX_LOCAL_APIC)
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#define physids_complement(dst, src) \
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bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC)
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#define physids_empty(map) \
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bitmap_empty((map).mask, MAX_LOCAL_APIC)
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#define physids_equal(map1, map2) \
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bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC)
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#define physids_weight(map) \
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bitmap_weight((map).mask, MAX_LOCAL_APIC)
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#define physids_shift_right(d, s, n) \
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bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC)
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#define physids_shift_left(d, s, n) \
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bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC)
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static inline unsigned long physids_coerce(physid_mask_t *map)
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{
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return map->mask[0];
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}
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static inline void physids_promote(unsigned long physids, physid_mask_t *map)
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{
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physids_clear(*map);
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map->mask[0] = physids;
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}
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static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
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{
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physids_clear(*map);
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physid_set(physid, *map);
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}
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#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
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#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
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extern physid_mask_t phys_cpu_present_map;
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extern int generic_mps_oem_check(struct mpc_table *, char *, char *);
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extern int default_acpi_madt_oem_check(char *, char *);
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#endif /* _ASM_X86_MPSPEC_H */
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