forked from luck/tmp_suning_uos_patched
96a6b9ad05
Tell the PCI core about host bridge address translation so it can take care of bus-to-resource conversion for us. Here's the wrinkle on Cobalt: we can't generate normal I/O port addresses on PCI because the GT-64111 doesn't do any address translation, so we have this: CPU I/O port addresses [io 0x0000-0xffffff] PCI bus I/O port addresses [io 0x10000000-0x10ffffff] Legacy-mode IDE controllers start out with the legacy bus addresses, e.g., 0x1f0, assigned by pci_setup_device(). These are outside the range of addresses GT-64111 can generate on PCI, but pcibios_fixup_device_resources() converted them to CPU addresses anyway by adding io_offset. Therefore, we had to pre-adjust them in cobalt_legacy_ide_fixup(). With io_offset = 0xf0000000, we had this: res->start = 0x1f0 initialized in pci_setup_device() res->start = 0x100001f0 -= io_offset in cobalt_legacy_ide_fixup() res->start = 0x1f0 += io_offset in pcibios_fixup_device_resources() The difference after this patch is that the generic pci_bus_to_resource() only adds the offset if the bus address is inside a host bridge window. Since 0x1f0 is not a valid bus address and is not inside any windows, it is unaffected, so we now have this: region->start = 0x1f0 initialized in pci_setup_device() res->start = 0x1f0 no offset by pci_bus_to_resource() That means we can remove both pcibios_fixup_device_resources() and cobalt_legacy_ide_fixup(). I would *rather* set the host bridge offset to zero (which corresponds to what the GT-64111 actually does), and have both CPU and PCI addresses of [io 0x10000000-0x10ffffff]. However, that would require changes to generic code that assumes legacy I/O addresses, such as pic1_io_resource ([io 0x0020-0x00021]), and we'd have to keep a Cobalt IDE fixup. Of course, none of this changes the fact that references to I/O port 0x1f0 actually go to port 0x100001f0, not 0x1f0, on the Cobalt PCI bus. Fortunately the VT82C586 IDE controller only decodes the low 24 address bits, so it does work. CC: Ralf Baechle <ralf@linux-mips.org> CC: Yoichi Yuasa <yuasa@linux-mips.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> |
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| .. | ||
| fixup-bcm63xx.c | ||
| fixup-capcella.c | ||
| fixup-cobalt.c | ||
| fixup-emma2rh.c | ||
| fixup-fuloong2e.c | ||
| fixup-ip32.c | ||
| fixup-jmr3927.c | ||
| fixup-lemote2f.c | ||
| fixup-malta.c | ||
| fixup-mpc30x.c | ||
| fixup-pmcmsp.c | ||
| fixup-pnx8550.c | ||
| fixup-rbtx4927.c | ||
| fixup-rbtx4938.c | ||
| fixup-rc32434.c | ||
| fixup-sb1250.c | ||
| fixup-sni.c | ||
| fixup-tb0219.c | ||
| fixup-tb0226.c | ||
| fixup-tb0287.c | ||
| fixup-wrppmc.c | ||
| fixup-yosemite.c | ||
| Makefile | ||
| msi-octeon.c | ||
| ops-bcm63xx.c | ||
| ops-bonito64.c | ||
| ops-bridge.c | ||
| ops-emma2rh.c | ||
| ops-gt64xxx_pci0.c | ||
| ops-lantiq.c | ||
| ops-loongson2.c | ||
| ops-mace.c | ||
| ops-msc.c | ||
| ops-nile4.c | ||
| ops-pmcmsp.c | ||
| ops-pnx8550.c | ||
| ops-rc32434.c | ||
| ops-sni.c | ||
| ops-titan-ht.c | ||
| ops-titan.c | ||
| ops-tx3927.c | ||
| ops-tx4927.c | ||
| ops-vr41xx.c | ||
| pci-alchemy.c | ||
| pci-ath724x.c | ||
| pci-bcm47xx.c | ||
| pci-bcm63xx.c | ||
| pci-bcm63xx.h | ||
| pci-bcm1480.c | ||
| pci-bcm1480ht.c | ||
| pci-emma2rh.c | ||
| pci-ip27.c | ||
| pci-ip32.c | ||
| pci-lantiq.c | ||
| pci-lantiq.h | ||
| pci-lasat.c | ||
| pci-octeon.c | ||
| pci-rc32434.c | ||
| pci-sb1250.c | ||
| pci-tx4927.c | ||
| pci-tx4938.c | ||
| pci-tx4939.c | ||
| pci-vr41xx.c | ||
| pci-vr41xx.h | ||
| pci-xlr.c | ||
| pci-yosemite.c | ||
| pci.c | ||
| pcie-octeon.c | ||