forked from luck/tmp_suning_uos_patched
96d389ca10
On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device load and a store exclusive or PAR_EL1 read can cause a deadlock. The workaround requires a DMB SY before and after a PAR_EL1 register read. In addition, it's possible an interrupt (doing a device read) or KVM guest exit could be taken between the DMB and PAR read, so we also need a DMB before returning from interrupt and before returning to a guest. A deadlock is still possible with the workaround as KVM guests must also have the workaround. IOW, a malicious guest can deadlock an affected systems. This workaround also depends on a firmware counterpart to enable the h/w to insert DMB SY after load and store exclusive instructions. See the errata document SDEN-1152370 v10 [1] for more information. [1] https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Julien Thierry <julien.thierry.kdev@gmail.com> Cc: kvmarm@lists.cs.columbia.edu Link: https://lore.kernel.org/r/20201028182839.166037-2-robh@kernel.org Signed-off-by: Will Deacon <will@kernel.org> |
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| .. | ||
| acpi_object_usage.rst | ||
| amu.rst | ||
| arm-acpi.rst | ||
| booting.rst | ||
| cpu-feature-registers.rst | ||
| elf_hwcaps.rst | ||
| hugetlbpage.rst | ||
| index.rst | ||
| kasan-offsets.sh | ||
| legacy_instructions.rst | ||
| memory-tagging-extension.rst | ||
| memory.rst | ||
| perf.rst | ||
| pointer-authentication.rst | ||
| silicon-errata.rst | ||
| sve.rst | ||
| tagged-address-abi.rst | ||
| tagged-pointers.rst | ||