forked from luck/tmp_suning_uos_patched
55fd766b5f
On Freescale parts typically have TLB array for large mappings that we can bolt the linear mapping into. We utilize the code that already exists on PPC32 on the 64-bit side to setup the linear mapping to be cover by bolted TLB entries. We utilize a quarter of the variable size TLB array for this purpose. Additionally, we limit the amount of memory to what we can cover via bolted entries so we don't get secondary faults in the TLB miss handlers. We should fix this limitation in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
397 lines
8.6 KiB
ArmAsm
397 lines
8.6 KiB
ArmAsm
/*
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* This file contains low-level functions for performing various
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* types of TLB invalidations on various processors with no hash
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* table.
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*
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* This file implements the following functions for all no-hash
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* processors. Some aren't implemented for some variants. Some
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* are inline in tlbflush.h
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*
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* - tlbil_va
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* - tlbil_pid
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* - tlbil_all
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* - tlbivax_bcast
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*
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* Code mostly moved over from misc_32.S
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*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Partially rewritten by Cort Dougan (cort@cs.nmt.edu)
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* Paul Mackerras, Kumar Gala and Benjamin Herrenschmidt.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor.h>
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#include <asm/bug.h>
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#if defined(CONFIG_40x)
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/*
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* 40x implementation needs only tlbil_va
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*/
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_GLOBAL(__tlbil_va)
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/* We run the search with interrupts disabled because we have to change
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* the PID and I don't want to preempt when that happens.
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*/
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mfmsr r5
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mfspr r6,SPRN_PID
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wrteei 0
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mtspr SPRN_PID,r4
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tlbsx. r3, 0, r3
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mtspr SPRN_PID,r6
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wrtee r5
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bne 1f
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sync
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/* There are only 64 TLB entries, so r3 < 64, which means bit 25 is
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* clear. Since 25 is the V bit in the TLB_TAG, loading this value
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* will invalidate the TLB entry. */
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tlbwe r3, r3, TLB_TAG
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isync
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1: blr
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#elif defined(CONFIG_8xx)
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/*
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* Nothing to do for 8xx, everything is inline
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*/
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#elif defined(CONFIG_44x) /* Includes 47x */
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/*
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* 440 implementation uses tlbsx/we for tlbil_va and a full sweep
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* of the TLB for everything else.
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*/
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_GLOBAL(__tlbil_va)
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mfspr r5,SPRN_MMUCR
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mfmsr r10
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/*
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* We write 16 bits of STID since 47x supports that much, we
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* will never be passed out of bounds values on 440 (hopefully)
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*/
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rlwimi r5,r4,0,16,31
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/* We have to run the search with interrupts disabled, otherwise
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* an interrupt which causes a TLB miss can clobber the MMUCR
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* between the mtspr and the tlbsx.
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*
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* Critical and Machine Check interrupts take care of saving
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* and restoring MMUCR, so only normal interrupts have to be
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* taken care of.
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*/
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wrteei 0
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mtspr SPRN_MMUCR,r5
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tlbsx. r6,0,r3
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bne 10f
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sync
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BEGIN_MMU_FTR_SECTION
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b 2f
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
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/* On 440 There are only 64 TLB entries, so r3 < 64, which means bit
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* 22, is clear. Since 22 is the V bit in the TLB_PAGEID, loading this
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* value will invalidate the TLB entry.
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*/
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tlbwe r6,r6,PPC44x_TLB_PAGEID
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isync
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10: wrtee r10
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blr
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2:
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#ifdef CONFIG_PPC_47x
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oris r7,r6,0x8000 /* specify way explicitely */
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clrrwi r4,r3,12 /* get an EPN for the hashing with V = 0 */
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ori r4,r4,PPC47x_TLBE_SIZE
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tlbwe r4,r7,0 /* write it */
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isync
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wrtee r10
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blr
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#else /* CONFIG_PPC_47x */
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1: trap
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EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
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#endif /* !CONFIG_PPC_47x */
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_GLOBAL(_tlbil_all)
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_GLOBAL(_tlbil_pid)
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BEGIN_MMU_FTR_SECTION
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b 2f
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
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li r3,0
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sync
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/* Load high watermark */
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lis r4,tlb_44x_hwater@ha
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lwz r5,tlb_44x_hwater@l(r4)
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1: tlbwe r3,r3,PPC44x_TLB_PAGEID
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addi r3,r3,1
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cmpw 0,r3,r5
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ble 1b
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isync
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blr
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2:
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#ifdef CONFIG_PPC_47x
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/* 476 variant. There's not simple way to do this, hopefully we'll
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* try to limit the amount of such full invalidates
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*/
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mfmsr r11 /* Interrupts off */
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wrteei 0
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li r3,-1 /* Current set */
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lis r10,tlb_47x_boltmap@h
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ori r10,r10,tlb_47x_boltmap@l
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lis r7,0x8000 /* Specify way explicitely */
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b 9f /* For each set */
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1: li r9,4 /* Number of ways */
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li r4,0 /* Current way */
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li r6,0 /* Default entry value 0 */
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andi. r0,r8,1 /* Check if way 0 is bolted */
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mtctr r9 /* Load way counter */
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bne- 3f /* Bolted, skip loading it */
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2: /* For each way */
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or r5,r3,r4 /* Make way|index for tlbre */
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rlwimi r5,r5,16,8,15 /* Copy index into position */
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tlbre r6,r5,0 /* Read entry */
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3: addis r4,r4,0x2000 /* Next way */
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andi. r0,r6,PPC47x_TLB0_VALID /* Valid entry ? */
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beq 4f /* Nope, skip it */
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rlwimi r7,r5,0,1,2 /* Insert way number */
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rlwinm r6,r6,0,21,19 /* Clear V */
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tlbwe r6,r7,0 /* Write it */
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4: bdnz 2b /* Loop for each way */
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srwi r8,r8,1 /* Next boltmap bit */
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9: cmpwi cr1,r3,255 /* Last set done ? */
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addi r3,r3,1 /* Next set */
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beq cr1,1f /* End of loop */
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andi. r0,r3,0x1f /* Need to load a new boltmap word ? */
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bne 1b /* No, loop */
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lwz r8,0(r10) /* Load boltmap entry */
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addi r10,r10,4 /* Next word */
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b 1b /* Then loop */
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1: isync /* Sync shadows */
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wrtee r11
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#else /* CONFIG_PPC_47x */
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1: trap
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EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
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#endif /* !CONFIG_PPC_47x */
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blr
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#ifdef CONFIG_PPC_47x
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/*
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* _tlbivax_bcast is only on 47x. We don't bother doing a runtime
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* check though, it will blow up soon enough if we mistakenly try
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* to use it on a 440.
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*/
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_GLOBAL(_tlbivax_bcast)
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mfspr r5,SPRN_MMUCR
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mfmsr r10
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rlwimi r5,r4,0,16,31
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wrteei 0
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mtspr SPRN_MMUCR,r5
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isync
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/* tlbivax 0,r3 - use .long to avoid binutils deps */
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.long 0x7c000624 | (r3 << 11)
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isync
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eieio
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tlbsync
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sync
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wrtee r10
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blr
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#endif /* CONFIG_PPC_47x */
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#elif defined(CONFIG_FSL_BOOKE)
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/*
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* FSL BookE implementations.
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*
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* Since feature sections are using _SECTION_ELSE we need
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* to have the larger code path before the _SECTION_ELSE
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*/
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/*
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* Flush MMU TLB on the local processor
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*/
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_GLOBAL(_tlbil_all)
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BEGIN_MMU_FTR_SECTION
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li r3,(MMUCSR0_TLBFI)@l
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mtspr SPRN_MMUCSR0, r3
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1:
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mfspr r3,SPRN_MMUCSR0
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andi. r3,r3,MMUCSR0_TLBFI@l
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bne 1b
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MMU_FTR_SECTION_ELSE
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PPC_TLBILX_ALL(0,0)
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
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msync
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isync
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blr
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_GLOBAL(_tlbil_pid)
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BEGIN_MMU_FTR_SECTION
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slwi r3,r3,16
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mfmsr r10
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wrteei 0
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mfspr r4,SPRN_MAS6 /* save MAS6 */
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mtspr SPRN_MAS6,r3
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PPC_TLBILX_PID(0,0)
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mtspr SPRN_MAS6,r4 /* restore MAS6 */
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wrtee r10
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MMU_FTR_SECTION_ELSE
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li r3,(MMUCSR0_TLBFI)@l
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mtspr SPRN_MMUCSR0, r3
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1:
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mfspr r3,SPRN_MMUCSR0
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andi. r3,r3,MMUCSR0_TLBFI@l
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bne 1b
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ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBILX)
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msync
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isync
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blr
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/*
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* Flush MMU TLB for a particular address, but only on the local processor
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* (no broadcast)
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*/
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_GLOBAL(__tlbil_va)
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mfmsr r10
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wrteei 0
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slwi r4,r4,16
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ori r4,r4,(MAS6_ISIZE(BOOK3E_PAGESZ_4K))@l
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mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
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BEGIN_MMU_FTR_SECTION
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tlbsx 0,r3
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mfspr r4,SPRN_MAS1 /* check valid */
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andis. r3,r4,MAS1_VALID@h
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beq 1f
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rlwinm r4,r4,0,1,31
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mtspr SPRN_MAS1,r4
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tlbwe
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MMU_FTR_SECTION_ELSE
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PPC_TLBILX_VA(0,r3)
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
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msync
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isync
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1: wrtee r10
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blr
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#elif defined(CONFIG_PPC_BOOK3E)
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/*
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* New Book3E (>= 2.06) implementation
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*
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* Note: We may be able to get away without the interrupt masking stuff
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* if we save/restore MAS6 on exceptions that might modify it
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*/
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_GLOBAL(_tlbil_pid)
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slwi r4,r3,MAS6_SPID_SHIFT
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mfmsr r10
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wrteei 0
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mtspr SPRN_MAS6,r4
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PPC_TLBILX_PID(0,0)
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wrtee r10
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msync
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isync
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blr
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_GLOBAL(_tlbil_pid_noind)
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slwi r4,r3,MAS6_SPID_SHIFT
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mfmsr r10
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ori r4,r4,MAS6_SIND
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wrteei 0
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mtspr SPRN_MAS6,r4
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PPC_TLBILX_PID(0,0)
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wrtee r10
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msync
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isync
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blr
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_GLOBAL(_tlbil_all)
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PPC_TLBILX_ALL(0,0)
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msync
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isync
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blr
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_GLOBAL(_tlbil_va)
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mfmsr r10
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wrteei 0
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cmpwi cr0,r6,0
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slwi r4,r4,MAS6_SPID_SHIFT
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rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
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beq 1f
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rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
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1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
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PPC_TLBILX_VA(0,r3)
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msync
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isync
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wrtee r10
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blr
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_GLOBAL(_tlbivax_bcast)
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mfmsr r10
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wrteei 0
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cmpwi cr0,r6,0
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slwi r4,r4,MAS6_SPID_SHIFT
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rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
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beq 1f
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rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
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1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
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PPC_TLBIVAX(0,r3)
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eieio
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tlbsync
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sync
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wrtee r10
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blr
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_GLOBAL(set_context)
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#ifdef CONFIG_BDI_SWITCH
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/* Context switch the PTE pointer for the Abatron BDI2000.
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* The PGDIR is the second parameter.
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*/
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lis r5, abatron_pteptrs@h
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ori r5, r5, abatron_pteptrs@l
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stw r4, 0x4(r5)
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#endif
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mtspr SPRN_PID,r3
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isync /* Force context change */
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blr
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#else
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#error Unsupported processor type !
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#endif
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#if defined(CONFIG_PPC_FSL_BOOK3E)
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/*
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* extern void loadcam_entry(unsigned int index)
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*
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* Load TLBCAM[index] entry in to the L2 CAM MMU
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*/
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_GLOBAL(loadcam_entry)
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LOAD_REG_ADDR(r4, TLBCAM)
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mulli r5,r3,TLBCAM_SIZE
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add r3,r5,r4
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lwz r4,TLBCAM_MAS0(r3)
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mtspr SPRN_MAS0,r4
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lwz r4,TLBCAM_MAS1(r3)
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mtspr SPRN_MAS1,r4
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PPC_LL r4,TLBCAM_MAS2(r3)
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mtspr SPRN_MAS2,r4
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lwz r4,TLBCAM_MAS3(r3)
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mtspr SPRN_MAS3,r4
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BEGIN_MMU_FTR_SECTION
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lwz r4,TLBCAM_MAS7(r3)
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mtspr SPRN_MAS7,r4
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
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isync
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tlbwe
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isync
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blr
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#endif
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