forked from luck/tmp_suning_uos_patched
15e4db7b80
Defines for the S3C2443 DMA source selection, and update the maximum channels to 6 if the S3C2443 is selected. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
453 lines
13 KiB
C
453 lines
13 KiB
C
/* linux/include/asm-arm/arch-s3c2410/dma.h
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*
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* Copyright (C) 2003,2004,2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Samsung S3C241XX DMA support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_DMA_H
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#define __ASM_ARCH_DMA_H __FILE__
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#include <linux/sysdev.h>
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#include <asm/hardware.h>
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/*
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* This is the maximum DMA address(physical address) that can be DMAd to.
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*
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*/
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#define MAX_DMA_ADDRESS 0x40000000
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#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
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/* We use `virtual` dma channels to hide the fact we have only a limited
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* number of DMA channels, and not of all of them (dependant on the device)
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* can be attached to any DMA source. We therefore let the DMA core handle
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* the allocation of hardware channels to clients.
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*/
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enum dma_ch {
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DMACH_XD0,
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DMACH_XD1,
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DMACH_SDI,
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DMACH_SPI0,
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DMACH_SPI1,
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DMACH_UART0,
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DMACH_UART1,
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DMACH_UART2,
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DMACH_TIMER,
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DMACH_I2S_IN,
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DMACH_I2S_OUT,
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DMACH_PCM_IN,
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DMACH_PCM_OUT,
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DMACH_MIC_IN,
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DMACH_USB_EP1,
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DMACH_USB_EP2,
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DMACH_USB_EP3,
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DMACH_USB_EP4,
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DMACH_UART0_SRC2, /* s3c2412 second uart sources */
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DMACH_UART1_SRC2,
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DMACH_UART2_SRC2,
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DMACH_UART3, /* s3c2443 has extra uart */
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DMACH_UART3_SRC2,
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DMACH_MAX, /* the end entry */
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};
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#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
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/* we have 4 dma channels */
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#ifndef CONFIG_CPU_S3C2443
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#define S3C2410_DMA_CHANNELS (4)
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#else
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#define S3C2410_DMA_CHANNELS (6)
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#endif
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/* types */
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enum s3c2410_dma_state {
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S3C2410_DMA_IDLE,
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S3C2410_DMA_RUNNING,
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S3C2410_DMA_PAUSED
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};
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/* enum s3c2410_dma_loadst
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*
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* This represents the state of the DMA engine, wrt to the loaded / running
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* transfers. Since we don't have any way of knowing exactly the state of
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* the DMA transfers, we need to know the state to make decisions on wether
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* we can
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*
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* S3C2410_DMA_NONE
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*
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* There are no buffers loaded (the channel should be inactive)
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*
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* S3C2410_DMA_1LOADED
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*
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* There is one buffer loaded, however it has not been confirmed to be
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* loaded by the DMA engine. This may be because the channel is not
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* yet running, or the DMA driver decided that it was too costly to
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* sit and wait for it to happen.
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*
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* S3C2410_DMA_1RUNNING
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*
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* The buffer has been confirmed running, and not finisged
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*
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* S3C2410_DMA_1LOADED_1RUNNING
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*
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* There is a buffer waiting to be loaded by the DMA engine, and one
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* currently running.
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*/
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enum s3c2410_dma_loadst {
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S3C2410_DMALOAD_NONE,
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S3C2410_DMALOAD_1LOADED,
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S3C2410_DMALOAD_1RUNNING,
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S3C2410_DMALOAD_1LOADED_1RUNNING,
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};
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enum s3c2410_dma_buffresult {
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S3C2410_RES_OK,
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S3C2410_RES_ERR,
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S3C2410_RES_ABORT
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};
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enum s3c2410_dmasrc {
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S3C2410_DMASRC_HW, /* source is memory */
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S3C2410_DMASRC_MEM /* source is hardware */
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};
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/* enum s3c2410_chan_op
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*
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* operation codes passed to the DMA code by the user, and also used
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* to inform the current channel owner of any changes to the system state
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*/
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enum s3c2410_chan_op {
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S3C2410_DMAOP_START,
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S3C2410_DMAOP_STOP,
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S3C2410_DMAOP_PAUSE,
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S3C2410_DMAOP_RESUME,
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S3C2410_DMAOP_FLUSH,
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S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
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S3C2410_DMAOP_STARTED, /* indicate channel started */
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};
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/* flags */
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#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
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* waiting for reloads */
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#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
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/* dma buffer */
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struct s3c2410_dma_client {
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char *name;
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};
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/* s3c2410_dma_buf_s
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*
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* internally used buffer structure to describe a queued or running
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* buffer.
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*/
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struct s3c2410_dma_buf;
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struct s3c2410_dma_buf {
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struct s3c2410_dma_buf *next;
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int magic; /* magic */
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int size; /* buffer size in bytes */
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dma_addr_t data; /* start of DMA data */
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dma_addr_t ptr; /* where the DMA got to [1] */
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void *id; /* client's id */
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};
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/* [1] is this updated for both recv/send modes? */
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struct s3c2410_dma_chan;
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/* s3c2410_dma_cbfn_t
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*
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* buffer callback routine type
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*/
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typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
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void *buf, int size,
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enum s3c2410_dma_buffresult result);
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typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
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enum s3c2410_chan_op );
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struct s3c2410_dma_stats {
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unsigned long loads;
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unsigned long timeout_longest;
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unsigned long timeout_shortest;
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unsigned long timeout_avg;
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unsigned long timeout_failed;
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};
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struct s3c2410_dma_map;
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/* struct s3c2410_dma_chan
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*
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* full state information for each DMA channel
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*/
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struct s3c2410_dma_chan {
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/* channel state flags and information */
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unsigned char number; /* number of this dma channel */
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unsigned char in_use; /* channel allocated */
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unsigned char irq_claimed; /* irq claimed for channel */
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unsigned char irq_enabled; /* irq enabled for channel */
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unsigned char xfer_unit; /* size of an transfer */
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/* channel state */
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enum s3c2410_dma_state state;
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enum s3c2410_dma_loadst load_state;
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struct s3c2410_dma_client *client;
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/* channel configuration */
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enum s3c2410_dmasrc source;
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unsigned long dev_addr;
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unsigned long load_timeout;
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unsigned int flags; /* channel flags */
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struct s3c24xx_dma_map *map; /* channel hw maps */
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/* channel's hardware position and configuration */
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void __iomem *regs; /* channels registers */
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void __iomem *addr_reg; /* data address register */
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unsigned int irq; /* channel irq */
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unsigned long dcon; /* default value of DCON */
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/* driver handles */
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s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
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s3c2410_dma_opfn_t op_fn; /* channel op callback */
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/* stats gathering */
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struct s3c2410_dma_stats *stats;
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struct s3c2410_dma_stats stats_store;
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/* buffer list and information */
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struct s3c2410_dma_buf *curr; /* current dma buffer */
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struct s3c2410_dma_buf *next; /* next buffer to load */
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struct s3c2410_dma_buf *end; /* end of queue */
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/* system device */
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struct sys_device dev;
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};
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/* the currently allocated channel information */
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extern struct s3c2410_dma_chan s3c2410_chans[];
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/* note, we don't really use dma_device_t at the moment */
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typedef unsigned long dma_device_t;
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/* functions --------------------------------------------------------------- */
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/* s3c2410_dma_request
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*
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* request a dma channel exclusivley
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*/
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extern int s3c2410_dma_request(dmach_t channel,
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struct s3c2410_dma_client *, void *dev);
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/* s3c2410_dma_ctrl
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*
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* change the state of the dma channel
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*/
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extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
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/* s3c2410_dma_setflags
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*
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* set the channel's flags to a given state
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*/
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extern int s3c2410_dma_setflags(dmach_t channel,
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unsigned int flags);
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/* s3c2410_dma_free
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*
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* free the dma channel (will also abort any outstanding operations)
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*/
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extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
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/* s3c2410_dma_enqueue
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*
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* place the given buffer onto the queue of operations for the channel.
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* The buffer must be allocated from dma coherent memory, or the Dcache/WB
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* drained before the buffer is given to the DMA system.
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*/
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extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
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dma_addr_t data, int size);
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/* s3c2410_dma_config
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*
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* configure the dma channel
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*/
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extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
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/* s3c2410_dma_devconfig
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*
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* configure the device we're talking to
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*/
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extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
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int hwcfg, unsigned long devaddr);
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/* s3c2410_dma_getposition
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*
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* get the position that the dma transfer is currently at
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*/
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extern int s3c2410_dma_getposition(dmach_t channel,
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dma_addr_t *src, dma_addr_t *dest);
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extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
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extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
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/* DMA Register definitions */
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#define S3C2410_DMA_DISRC (0x00)
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#define S3C2410_DMA_DISRCC (0x04)
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#define S3C2410_DMA_DIDST (0x08)
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#define S3C2410_DMA_DIDSTC (0x0C)
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#define S3C2410_DMA_DCON (0x10)
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#define S3C2410_DMA_DSTAT (0x14)
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#define S3C2410_DMA_DCSRC (0x18)
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#define S3C2410_DMA_DCDST (0x1C)
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#define S3C2410_DMA_DMASKTRIG (0x20)
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#define S3C2412_DMA_DMAREQSEL (0x24)
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#define S3C2443_DMA_DMAREQSEL (0x24)
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#define S3C2410_DISRCC_INC (1<<0)
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#define S3C2410_DISRCC_APB (1<<1)
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#define S3C2410_DMASKTRIG_STOP (1<<2)
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#define S3C2410_DMASKTRIG_ON (1<<1)
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#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
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#define S3C2410_DCON_DEMAND (0<<31)
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#define S3C2410_DCON_HANDSHAKE (1<<31)
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#define S3C2410_DCON_SYNC_PCLK (0<<30)
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#define S3C2410_DCON_SYNC_HCLK (1<<30)
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#define S3C2410_DCON_INTREQ (1<<29)
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#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
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#define S3C2410_DCON_CH0_UART0 (1<<24)
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#define S3C2410_DCON_CH0_SDI (2<<24)
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#define S3C2410_DCON_CH0_TIMER (3<<24)
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#define S3C2410_DCON_CH0_USBEP1 (4<<24)
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#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
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#define S3C2410_DCON_CH1_UART1 (1<<24)
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#define S3C2410_DCON_CH1_I2SSDI (2<<24)
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#define S3C2410_DCON_CH1_SPI (3<<24)
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#define S3C2410_DCON_CH1_USBEP2 (4<<24)
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#define S3C2410_DCON_CH2_I2SSDO (0<<24)
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#define S3C2410_DCON_CH2_I2SSDI (1<<24)
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#define S3C2410_DCON_CH2_SDI (2<<24)
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#define S3C2410_DCON_CH2_TIMER (3<<24)
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#define S3C2410_DCON_CH2_USBEP3 (4<<24)
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#define S3C2410_DCON_CH3_UART2 (0<<24)
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#define S3C2410_DCON_CH3_SDI (1<<24)
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#define S3C2410_DCON_CH3_SPI (2<<24)
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#define S3C2410_DCON_CH3_TIMER (3<<24)
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#define S3C2410_DCON_CH3_USBEP4 (4<<24)
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#define S3C2410_DCON_SRCSHIFT (24)
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#define S3C2410_DCON_SRCMASK (7<<24)
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#define S3C2410_DCON_BYTE (0<<20)
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#define S3C2410_DCON_HALFWORD (1<<20)
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#define S3C2410_DCON_WORD (2<<20)
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#define S3C2410_DCON_AUTORELOAD (0<<22)
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#define S3C2410_DCON_NORELOAD (1<<22)
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#define S3C2410_DCON_HWTRIG (1<<23)
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#ifdef CONFIG_CPU_S3C2440
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#define S3C2440_DIDSTC_CHKINT (1<<2)
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#define S3C2440_DCON_CH0_I2SSDO (5<<24)
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#define S3C2440_DCON_CH0_PCMIN (6<<24)
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#define S3C2440_DCON_CH1_PCMOUT (5<<24)
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#define S3C2440_DCON_CH1_SDI (6<<24)
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#define S3C2440_DCON_CH2_PCMIN (5<<24)
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#define S3C2440_DCON_CH2_MICIN (6<<24)
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#define S3C2440_DCON_CH3_MICIN (5<<24)
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#define S3C2440_DCON_CH3_PCMOUT (6<<24)
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#endif
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#ifdef CONFIG_CPU_S3C2412
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#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
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#define S3C2412_DMAREQSEL_HW (1)
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#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
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#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
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#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
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#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
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#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
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#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
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#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
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#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
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#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
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#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
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#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
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#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
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#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
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#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
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#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
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#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
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#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
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#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
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#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
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#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
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#endif
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#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
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#define S3C2443_DMAREQSEL_HW (1)
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#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
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#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
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#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
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#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
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#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
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#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
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#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
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#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
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#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
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#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
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#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
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#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
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#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
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#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
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#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
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#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
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#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
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#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
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#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
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#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
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#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
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#endif /* __ASM_ARCH_DMA_H */
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