forked from luck/tmp_suning_uos_patched
567bb8fd47
There is nothing in these routines that inherently depends on R0 use.
Given that these routines are inlined, it is rather easy to blow up the
compiler by exhausting the spill class when performing a 64-bit swab.
This presently manifests itself as the following:
CC fs/ocfs2/suballoc.o
fs/ocfs2/suballoc.c: In function 'ocfs2_reserve_suballoc_bits':
fs/ocfs2/suballoc.c:638: error: unrecognizable insn:
(insn 2793 1230 1231 103 arch/sh/include/asm/swab.h:33 (set (reg:HI 853)
(subreg:HI (reg:SI 149 macl) 2)) -1 (expr_list:REG_DEAD (reg:SI 149 macl)
(nil)))
fs/ocfs2/suballoc.c:638: internal compiler error: in extract_insn, at recog.c:1991
This patch switches over to using an arbitrarily assigned register instead.
While the same issue does not exist in the SH-5 case, there is likewise no harm
in having an alternate register used for the byterev/shari pair.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
61 lines
1015 B
C
61 lines
1015 B
C
#ifndef __ASM_SH_SWAB_H
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#define __ASM_SH_SWAB_H
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/*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2000, 2001 Paolo Alberelli
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*/
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#include <linux/compiler.h>
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#include <linux/types.h>
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#define __SWAB_64_THRU_32__
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static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
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{
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__asm__(
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#ifdef __SH5__
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"byterev %1, %0\n\t"
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"shari %0, 32, %0"
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#else
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"swap.b %1, %0\n\t"
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"swap.w %0, %0\n\t"
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"swap.b %0, %0"
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#endif
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: "=r" (x)
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: "r" (x));
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return x;
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}
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#define __arch_swab32 __arch_swab32
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static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
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{
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__asm__(
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#ifdef __SH5__
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"byterev %1, %0\n\t"
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"shari %0, 32, %0"
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#else
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"swap.b %1, %0"
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#endif
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: "=r" (x)
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: "r" (x));
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return x;
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}
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#define __arch_swab16 __arch_swab16
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static inline __u64 __arch_swab64(__u64 val)
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{
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union {
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struct { __u32 a,b; } s;
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__u64 u;
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} v, w;
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v.u = val;
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w.s.b = __arch_swab32(v.s.a);
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w.s.a = __arch_swab32(v.s.b);
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return w.u;
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}
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#define __arch_swab64 __arch_swab64
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#endif /* __ASM_SH_SWAB_H */
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