forked from luck/tmp_suning_uos_patched
2231ef876a
The #defines in sun3_scsi.h are intended to influence subsequent #includes in sun3_scsi.c. IMHO, that's too convoluted. Move sun3_scsi.h macro definitions to sun3_scsi.c, consistent with other NCR5380 drivers. Omit the unused NCR5380_local_declare() and NCR5380_setup() macros. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Christoph Hellwig <hch@lst.de>
103 lines
3.0 KiB
C
103 lines
3.0 KiB
C
/*
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* Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
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*
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* Sun3 DMA additions by Sam Creasey (sammy@sammy.net)
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*
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* Adapted from mac_scsinew.h:
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*/
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/*
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* Cumana Generic NCR5380 driver defines
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*
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* Copyright 1993, Drew Eckhardt
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* Visionary Computing
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* (Unix and Linux consulting and custom programming)
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* drew@colorado.edu
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* +1 (303) 440-4894
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*/
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#ifndef SUN3_SCSI_H
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#define SUN3_SCSI_H
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/* additional registers - mainly DMA control regs */
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/* these start at regbase + 8 -- directly after the NCR regs */
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struct sun3_dma_regs {
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unsigned short dma_addr_hi; /* vme only */
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unsigned short dma_addr_lo; /* vme only */
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unsigned short dma_count_hi; /* vme only */
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unsigned short dma_count_lo; /* vme only */
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unsigned short udc_data; /* udc dma data reg (obio only) */
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unsigned short udc_addr; /* uda dma addr reg (obio only) */
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unsigned short fifo_data; /* fifo data reg, holds extra byte on
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odd dma reads */
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unsigned short fifo_count;
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unsigned short csr; /* control/status reg */
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unsigned short bpack_hi; /* vme only */
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unsigned short bpack_lo; /* vme only */
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unsigned short ivect; /* vme only */
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unsigned short fifo_count_hi; /* vme only */
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};
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/* ucd chip specific regs - live in dvma space */
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struct sun3_udc_regs {
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unsigned short rsel; /* select regs to load */
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unsigned short addr_hi; /* high word of addr */
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unsigned short addr_lo; /* low word */
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unsigned short count; /* words to be xfer'd */
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unsigned short mode_hi; /* high word of channel mode */
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unsigned short mode_lo; /* low word of channel mode */
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};
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/* addresses of the udc registers */
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#define UDC_MODE 0x38
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#define UDC_CSR 0x2e /* command/status */
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#define UDC_CHN_HI 0x26 /* chain high word */
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#define UDC_CHN_LO 0x22 /* chain lo word */
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#define UDC_CURA_HI 0x1a /* cur reg A high */
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#define UDC_CURA_LO 0x0a /* cur reg A low */
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#define UDC_CURB_HI 0x12 /* cur reg B high */
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#define UDC_CURB_LO 0x02 /* cur reg B low */
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#define UDC_MODE_HI 0x56 /* mode reg high */
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#define UDC_MODE_LO 0x52 /* mode reg low */
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#define UDC_COUNT 0x32 /* words to xfer */
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/* some udc commands */
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#define UDC_RESET 0
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#define UDC_CHN_START 0xa0 /* start chain */
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#define UDC_INT_ENABLE 0x32 /* channel 1 int on */
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/* udc mode words */
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#define UDC_MODE_HIWORD 0x40
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#define UDC_MODE_LSEND 0xc2
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#define UDC_MODE_LRECV 0xd2
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/* udc reg selections */
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#define UDC_RSEL_SEND 0x282
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#define UDC_RSEL_RECV 0x182
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/* bits in csr reg */
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#define CSR_DMA_ACTIVE 0x8000
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#define CSR_DMA_CONFLICT 0x4000
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#define CSR_DMA_BUSERR 0x2000
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#define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
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#define CSR_SDB_INT 0x200 /* sbc interrupt pending */
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#define CSR_DMA_INT 0x100 /* dma interrupt pending */
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#define CSR_LEFT 0xc0
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#define CSR_LEFT_3 0xc0
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#define CSR_LEFT_2 0x80
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#define CSR_LEFT_1 0x40
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#define CSR_PACK_ENABLE 0x20
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#define CSR_DMA_ENABLE 0x10
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#define CSR_SEND 0x8 /* 1 = send 0 = recv */
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#define CSR_FIFO 0x2 /* reset fifo */
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#define CSR_INTR 0x4 /* interrupt enable */
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#define CSR_SCSI 0x1
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#define VME_DATA24 0x3d00
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#endif /* SUN3_SCSI_H */
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