forked from luck/tmp_suning_uos_patched
f25f64ed5b
Due to index register access ordering problems, when using macros a line like this fails (and does nothing): setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88); With inlined functions this line will work as expected. Note about a side effect: Seems on Geode GX1 based systems the "suspend on halt power saving feature" was never enabled due to this wrong macro expansion. With inlined functions it will be enabled, but this will stop the TSC when the CPU runs into a HLT instruction. Kernel output something like this: Clocksource tsc unstable (delta = -472746897 ns) This is the 3rd version of this patch. - Adding missed arch/i386/kernel/cpu/mtrr/state.c Thanks to Andres Salomon - Adding some big fat comments into the new header file Suggested by Andi Kleen AK: fixed x86-64 compilation Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
31 lines
681 B
C
31 lines
681 B
C
/*
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* NSC/Cyrix CPU indexed register access. Must be inlined instead of
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* macros to ensure correct access ordering
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* Access order is always 0x22 (=offset), 0x23 (=value)
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*
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* When using the old macros a line like
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* setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
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* gets expanded to:
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* do {
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* outb((CX86_CCR2), 0x22);
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* outb((({
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* outb((CX86_CCR2), 0x22);
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* inb(0x23);
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* }) | 0x88), 0x23);
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* } while (0);
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*
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* which in fact violates the access order (= 0x22, 0x22, 0x23, 0x23).
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*/
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static inline u8 getCx86(u8 reg)
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{
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outb(reg, 0x22);
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return inb(0x23);
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}
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static inline void setCx86(u8 reg, u8 data)
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{
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outb(reg, 0x22);
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outb(data, 0x23);
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}
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