forked from luck/tmp_suning_uos_patched
3edf22ab34
MPCore platform This patch adds the registration of the secondary GIC on the baseboard, together with the IRQ chaining setup. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
122 lines
4.9 KiB
C
122 lines
4.9 KiB
C
/*
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* linux/include/asm-arm/arch-realview/irqs.h
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*
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* Copyright (C) 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <asm/arch/platform.h>
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#define IRQ_LOCALTIMER 29
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#define IRQ_LOCALWDOG 30
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/*
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* IRQ interrupts definitions are the same the INT definitions
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* held within platform.h
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*/
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#define IRQ_GIC_START 32
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#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT)
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#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT)
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#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx)
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#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx)
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#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1)
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#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3)
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#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0)
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#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1)
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#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2)
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#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3)
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#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT)
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#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT)
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#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0)
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#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1)
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#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2)
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#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3)
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#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT)
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#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT)
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#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT)
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#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT)
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#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT)
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#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT)
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#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B)
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#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B)
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#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0)
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#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1)
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#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3)
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#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD)
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#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH)
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#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD)
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#define IRQ_DoC (IRQ_GIC_START + INT_DoC)
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#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A)
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#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A)
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#define IRQ_AACI (IRQ_GIC_START + INT_AACI)
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#define IRQ_ETH (IRQ_GIC_START + INT_ETH)
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#define IRQ_USB (IRQ_GIC_START + INT_USB)
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#define IRQ_PMU_CPU0 (IRQ_GIC_START + INT_PMU_CPU0)
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#define IRQ_PMU_CPU1 (IRQ_GIC_START + INT_PMU_CPU1)
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#define IRQ_PMU_CPU2 (IRQ_GIC_START + INT_PMU_CPU2)
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#define IRQ_PMU_CPU3 (IRQ_GIC_START + INT_PMU_CPU3)
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#define IRQ_PMU_SCU0 (IRQ_GIC_START + INT_PMU_SCU0)
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#define IRQ_PMU_SCU1 (IRQ_GIC_START + INT_PMU_SCU1)
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#define IRQ_PMU_SCU2 (IRQ_GIC_START + INT_PMU_SCU2)
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#define IRQ_PMU_SCU3 (IRQ_GIC_START + INT_PMU_SCU3)
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#define IRQ_PMU_SCU4 (IRQ_GIC_START + INT_PMU_SCU4)
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#define IRQ_PMU_SCU5 (IRQ_GIC_START + INT_PMU_SCU5)
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#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6)
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#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7)
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#define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1)
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#define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2)
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#define IRQMASK_WDOGINT INTMASK_WDOGINT
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#define IRQMASK_SOFTINT INTMASK_SOFTINT
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#define IRQMASK_COMMRx INTMASK_COMMRx
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#define IRQMASK_COMMTx INTMASK_COMMTx
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#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
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#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
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#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
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#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
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#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
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#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
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#define IRQMASK_RTCINT INTMASK_RTCINT
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#define IRQMASK_SSPINT INTMASK_SSPINT
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#define IRQMASK_UARTINT0 INTMASK_UARTINT0
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#define IRQMASK_UARTINT1 INTMASK_UARTINT1
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#define IRQMASK_UARTINT2 INTMASK_UARTINT2
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#define IRQMASK_SCIINT INTMASK_SCIINT
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#define IRQMASK_CLCDINT INTMASK_CLCDINT
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#define IRQMASK_DMAINT INTMASK_DMAINT
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#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
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#define IRQMASK_MBXINT INTMASK_MBXINT
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#define IRQMASK_GNDINT INTMASK_GNDINT
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#define IRQMASK_MMCI0B INTMASK_MMCI0B
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#define IRQMASK_MMCI1B INTMASK_MMCI1B
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#define IRQMASK_KMI0 INTMASK_KMI0
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#define IRQMASK_KMI1 INTMASK_KMI1
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#define IRQMASK_SCI3 INTMASK_SCI3
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#define IRQMASK_UART3 INTMASK_UART3
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#define IRQMASK_CLCD INTMASK_CLCD
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#define IRQMASK_TOUCH INTMASK_TOUCH
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#define IRQMASK_KEYPAD INTMASK_KEYPAD
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#define IRQMASK_DoC INTMASK_DoC
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#define IRQMASK_MMCI0A INTMASK_MMCI0A
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#define IRQMASK_MMCI1A INTMASK_MMCI1A
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#define IRQMASK_AACI INTMASK_AACI
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#define IRQMASK_ETH INTMASK_ETH
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#define IRQMASK_USB INTMASK_USB
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#define NR_IRQS (IRQ_GIC_START + 96)
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