forked from luck/tmp_suning_uos_patched
3176bf2d7c
Add sysclk auto mode. When it's sysclk auto mode, if the MCLK is available for clock configure, using MCLK to provide sysclk directly, otherwise, search a available pll out frequcncy and set pll. Configure clock in hw_params may cause problems when using bypass style paths without hw_params in machine driver getting called. So add configure clock to set_bias_level. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@kernel.org>
115 lines
2.8 KiB
C
115 lines
2.8 KiB
C
/*
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* wm8960.h -- WM8960 Soc Audio driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _WM8960_H
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#define _WM8960_H
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/* WM8960 register space */
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#define WM8960_CACHEREGNUM 56
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#define WM8960_LINVOL 0x0
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#define WM8960_RINVOL 0x1
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#define WM8960_LOUT1 0x2
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#define WM8960_ROUT1 0x3
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#define WM8960_CLOCK1 0x4
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#define WM8960_DACCTL1 0x5
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#define WM8960_DACCTL2 0x6
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#define WM8960_IFACE1 0x7
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#define WM8960_CLOCK2 0x8
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#define WM8960_IFACE2 0x9
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#define WM8960_LDAC 0xa
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#define WM8960_RDAC 0xb
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#define WM8960_RESET 0xf
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#define WM8960_3D 0x10
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#define WM8960_ALC1 0x11
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#define WM8960_ALC2 0x12
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#define WM8960_ALC3 0x13
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#define WM8960_NOISEG 0x14
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#define WM8960_LADC 0x15
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#define WM8960_RADC 0x16
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#define WM8960_ADDCTL1 0x17
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#define WM8960_ADDCTL2 0x18
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#define WM8960_POWER1 0x19
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#define WM8960_POWER2 0x1a
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#define WM8960_ADDCTL3 0x1b
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#define WM8960_APOP1 0x1c
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#define WM8960_APOP2 0x1d
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#define WM8960_LINPATH 0x20
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#define WM8960_RINPATH 0x21
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#define WM8960_LOUTMIX 0x22
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#define WM8960_ROUTMIX 0x25
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#define WM8960_MONOMIX1 0x26
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#define WM8960_MONOMIX2 0x27
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#define WM8960_LOUT2 0x28
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#define WM8960_ROUT2 0x29
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#define WM8960_MONO 0x2a
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#define WM8960_INBMIX1 0x2b
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#define WM8960_INBMIX2 0x2c
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#define WM8960_BYPASS1 0x2d
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#define WM8960_BYPASS2 0x2e
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#define WM8960_POWER3 0x2f
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#define WM8960_ADDCTL4 0x30
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#define WM8960_CLASSD1 0x31
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#define WM8960_CLASSD3 0x33
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#define WM8960_PLL1 0x34
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#define WM8960_PLL2 0x35
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#define WM8960_PLL3 0x36
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#define WM8960_PLL4 0x37
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/*
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* WM8960 Clock dividers
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*/
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#define WM8960_SYSCLKDIV 0
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#define WM8960_DACDIV 1
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#define WM8960_OPCLKDIV 2
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#define WM8960_DCLKDIV 3
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#define WM8960_TOCLKSEL 4
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#define WM8960_SYSCLK_DIV_1 (0 << 1)
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#define WM8960_SYSCLK_DIV_2 (2 << 1)
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#define WM8960_SYSCLK_MCLK (0 << 0)
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#define WM8960_SYSCLK_PLL (1 << 0)
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#define WM8960_SYSCLK_AUTO (2 << 0)
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#define WM8960_DAC_DIV_1 (0 << 3)
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#define WM8960_DAC_DIV_1_5 (1 << 3)
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#define WM8960_DAC_DIV_2 (2 << 3)
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#define WM8960_DAC_DIV_3 (3 << 3)
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#define WM8960_DAC_DIV_4 (4 << 3)
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#define WM8960_DAC_DIV_5_5 (5 << 3)
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#define WM8960_DAC_DIV_6 (6 << 3)
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#define WM8960_DCLK_DIV_1_5 (0 << 6)
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#define WM8960_DCLK_DIV_2 (1 << 6)
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#define WM8960_DCLK_DIV_3 (2 << 6)
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#define WM8960_DCLK_DIV_4 (3 << 6)
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#define WM8960_DCLK_DIV_6 (4 << 6)
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#define WM8960_DCLK_DIV_8 (5 << 6)
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#define WM8960_DCLK_DIV_12 (6 << 6)
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#define WM8960_DCLK_DIV_16 (7 << 6)
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#define WM8960_TOCLK_F19 (0 << 1)
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#define WM8960_TOCLK_F21 (1 << 1)
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#define WM8960_OPCLK_DIV_1 (0 << 0)
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#define WM8960_OPCLK_DIV_2 (1 << 0)
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#define WM8960_OPCLK_DIV_3 (2 << 0)
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#define WM8960_OPCLK_DIV_4 (3 << 0)
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#define WM8960_OPCLK_DIV_5_5 (4 << 0)
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#define WM8960_OPCLK_DIV_6 (5 << 0)
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#endif
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