kernel_optimize_test/arch/sh/include
Paul Mundt 185aed7557 sh: Provide a sane valid_phys_addr_range() to prevent TLB reset with PMB.
With the PMB enabled, only P1SEG and up are covered by the PMB mappings,
meaning that situations where out-of-bounds physical addresses are read
from will lead to TLB reset after the PMB miss, allowing for use cases
like dd if=/dev/mem to reset the TLB.

Fix this up to make sure the reference is between __MEMORY_START (phys)
and __pa(high_memory). This is coherent across all variants of sh/sh64
with and without MMU, though the PMB bug itself is only applicable to
SH-4A parts.

Reported-by: Hideo Saito <saito@densan.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-11-12 12:53:48 +09:00
..
asm sh: Provide a sane valid_phys_addr_range() to prevent TLB reset with PMB. 2008-11-12 12:53:48 +09:00
cpu-common/cpu
cpu-sh2/cpu SH2(A) cache update 2008-08-04 16:33:47 +09:00
cpu-sh2a/cpu sh: Move the CPU definition headers from asm/ to cpu/. 2008-10-20 12:04:53 +09:00
cpu-sh3/cpu sh: Move the CPU definition headers from asm/ to cpu/. 2008-10-20 12:04:53 +09:00
cpu-sh4/cpu sh: Add on-chip RTC support for SH7722. 2008-10-28 18:40:19 +09:00
cpu-sh5/cpu
mach-common/mach sh: mach-highlander: Handle SCIF pinmuxing on R7785RP. 2008-10-23 12:35:43 +09:00
mach-dreamcast/mach
mach-landisk/mach
mach-se/mach
mach-sh03/mach