Atish Patra a37d56fc40 RISC-V: Use WRITE_ONCE instead of direct access ... The secondary harts spin on couple of per cpu variables until both of these are non-zero so it's not necessary to have any ordering here. However, WRITE_ONCE should be used to avoid tearing. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-10-22 17:03:37 -07:00
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configs	irqchip: add a SiFive PLIC driver	2018-08-13 08:31:32 -07:00
include	RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid	2018-10-22 17:03:36 -07:00
kernel	RISC-V: Use WRITE_ONCE instead of direct access	2018-10-22 17:03:37 -07:00
lib	RISC-V: implement __lshrti3.	2018-08-13 08:31:30 -07:00
mm	mm: convert return type of handle_mm_fault() caller to vm_fault_t	2018-08-17 16:20:28 -07:00
Kconfig	kconfig: include kernel/Kconfig.preempt from init/Kconfig	2018-08-02 08:06:54 +09:00
Kconfig.debug	Kconfig: consolidate the "Kernel hacking" menu	2018-08-02 08:06:48 +09:00
Makefile	kbuild: rename LDFLAGS to KBUILD_LDFLAGS	2018-08-24 08:22:08 +09:00