forked from luck/tmp_suning_uos_patched
789b23bc40
Here are the at91 specific files dedicated to the at91sam9g45 series. They mimic the traditional at91 way of managing chips & boards. The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES. In the future, the main board for this 9g45 series will be the AT91SAM9M10G45-EK (I choose this last name for the board file). Simple drivers are enabled in _devices and board- files. Newer peripheral support will be added in future patches. Incuded peripherals support (for now): - USART - SPI - Ethernet - NAND flash - LCD - gpio/joystick/buttons - leds and pwm Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
361 lines
8.5 KiB
C
361 lines
8.5 KiB
C
/*
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* Chip-specific setup code for the AT91SAM9G45 family
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*
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* Copyright (C) 2009 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/pm.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/at91sam9g45.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_rstc.h>
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#include <mach/at91_shdwc.h>
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#include "generic.h"
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#include "clock.h"
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static struct map_desc at91sam9g45_io_desc[] __initdata = {
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{
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.virtual = AT91_VA_BASE_SYS,
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.pfn = __phys_to_pfn(AT91_BASE_SYS),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE,
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.pfn = __phys_to_pfn(AT91SAM9G45_SRAM_BASE),
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.length = AT91SAM9G45_SRAM_SIZE,
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.type = MT_DEVICE,
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}
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};
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioDE_clk = {
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.name = "pioDE_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc0_clk = {
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.name = "mci0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi0_clk = {
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.name = "twi0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi1_clk = {
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.name = "twi1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc0_clk = {
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.name = "ssc0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc1_clk = {
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.name = "ssc1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tcb_clk = {
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.name = "tcb_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tsc_clk = {
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.name = "tsc_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TSC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma_clk = {
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.name = "dma_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_DMA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uhphs_clk = {
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.name = "uhphs_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ac97_clk = {
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.name = "ac97_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk macb_clk = {
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.name = "macb_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk isi_clk = {
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.name = "isi_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udphs_clk = {
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.name = "udphs_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc1_clk = {
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.name = "mci1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* One additional fake clock for ohci */
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static struct clk ohci_clk = {
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.name = "ohci_clk",
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.pmc_mask = 0,
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.type = CLK_TYPE_PERIPHERAL,
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.parent = &uhphs_clk,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&pioDE_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&usart3_clk,
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&mmc0_clk,
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&twi0_clk,
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&twi1_clk,
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&spi0_clk,
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&spi1_clk,
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&ssc0_clk,
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&ssc1_clk,
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&tcb_clk,
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&pwm_clk,
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&tsc_clk,
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&dma_clk,
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&uhphs_clk,
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&lcdc_clk,
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&ac97_clk,
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&macb_clk,
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&isi_clk,
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&udphs_clk,
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&mmc1_clk,
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// irq0
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&ohci_clk,
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9g45_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clk_register(&pck0);
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clk_register(&pck1);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91sam9g45_gpio[] = {
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{
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.id = AT91SAM9G45_ID_PIOA,
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.offset = AT91_PIOA,
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.clock = &pioA_clk,
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}, {
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.id = AT91SAM9G45_ID_PIOB,
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.offset = AT91_PIOB,
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.clock = &pioB_clk,
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}, {
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.id = AT91SAM9G45_ID_PIOC,
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.offset = AT91_PIOC,
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.clock = &pioC_clk,
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}, {
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.id = AT91SAM9G45_ID_PIODE,
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.offset = AT91_PIOD,
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.clock = &pioDE_clk,
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}, {
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.id = AT91SAM9G45_ID_PIODE,
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.offset = AT91_PIOE,
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.clock = &pioDE_clk,
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}
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};
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static void at91sam9g45_reset(void)
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{
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
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}
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static void at91sam9g45_poweroff(void)
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{
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at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
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}
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/* --------------------------------------------------------------------
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* AT91SAM9G45 processor initialization
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* -------------------------------------------------------------------- */
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void __init at91sam9g45_initialize(unsigned long main_clock)
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{
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/* Map peripherals */
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iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc));
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at91_arch_reset = at91sam9g45_reset;
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pm_power_off = at91sam9g45_poweroff;
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at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
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/* Init clock subsystem */
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at91_clock_init(main_clock);
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/* Register the processor-specific clocks */
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at91sam9g45_register_clocks();
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9g45_gpio, 5);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller (FIQ) */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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1, /* Parallel IO Controller D and E */
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0,
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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5, /* USART 3 */
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0, /* Multimedia Card Interface 0 */
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6, /* Two-Wire Interface 0 */
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6, /* Two-Wire Interface 1 */
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5, /* Serial Peripheral Interface 0 */
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5, /* Serial Peripheral Interface 1 */
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4, /* Serial Synchronous Controller 0 */
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4, /* Serial Synchronous Controller 1 */
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0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
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0, /* Pulse Width Modulation Controller */
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0, /* Touch Screen Controller */
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0, /* DMA Controller */
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2, /* USB Host High Speed port */
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3, /* LDC Controller */
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5, /* AC97 Controller */
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3, /* Ethernet */
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0, /* Image Sensor Interface */
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2, /* USB Device High speed port */
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0,
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0, /* Multimedia Card Interface 1 */
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0,
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0, /* Advanced Interrupt Controller (IRQ0) */
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};
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void __init at91sam9g45_init_interrupts(unsigned int priority[NR_AIC_IRQS])
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{
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if (!priority)
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priority = at91sam9g45_default_irq_priority;
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/* Initialize the AIC interrupt controller */
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at91_aic_init(priority);
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/* Enable GPIO interrupts */
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at91_gpio_irq_setup();
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}
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