forked from luck/tmp_suning_uos_patched
5095f59bda
Remove model information, encoding/decoding and reduce bookkeeping. This, besides removing a lot of code and cleaning up the code, also enables these features on many more CPUs that were enumerated before. Reported-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> LKML-Reference: <1244224637.8212.6.camel@ht.satnam> Signed-off-by: Ingo Molnar <mingo@elte.hu>
128 lines
3.7 KiB
C
128 lines
3.7 KiB
C
#ifndef _ASM_X86_CPU_DEBUG_H
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#define _ASM_X86_CPU_DEBUG_H
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/*
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* CPU x86 architecture debug
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*
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* Copyright(C) 2009 Jaswinder Singh Rajput
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*/
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/* Register flags */
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enum cpu_debug_bit {
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/* Model Specific Registers (MSRs) */
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CPU_MC_BIT, /* Machine Check */
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CPU_MONITOR_BIT, /* Monitor */
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CPU_TIME_BIT, /* Time */
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CPU_PMC_BIT, /* Performance Monitor */
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CPU_PLATFORM_BIT, /* Platform */
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CPU_APIC_BIT, /* APIC */
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CPU_POWERON_BIT, /* Power-on */
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CPU_CONTROL_BIT, /* Control */
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CPU_FEATURES_BIT, /* Features control */
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CPU_LBRANCH_BIT, /* Last Branch */
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CPU_BIOS_BIT, /* BIOS */
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CPU_FREQ_BIT, /* Frequency */
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CPU_MTTR_BIT, /* MTRR */
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CPU_PERF_BIT, /* Performance */
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CPU_CACHE_BIT, /* Cache */
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CPU_SYSENTER_BIT, /* Sysenter */
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CPU_THERM_BIT, /* Thermal */
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CPU_MISC_BIT, /* Miscellaneous */
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CPU_DEBUG_BIT, /* Debug */
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CPU_PAT_BIT, /* PAT */
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CPU_VMX_BIT, /* VMX */
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CPU_CALL_BIT, /* System Call */
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CPU_BASE_BIT, /* BASE Address */
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CPU_VER_BIT, /* Version ID */
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CPU_CONF_BIT, /* Configuration */
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CPU_SMM_BIT, /* System mgmt mode */
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CPU_SVM_BIT, /*Secure Virtual Machine*/
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CPU_OSVM_BIT, /* OS-Visible Workaround*/
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/* Standard Registers */
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CPU_TSS_BIT, /* Task Stack Segment */
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CPU_CR_BIT, /* Control Registers */
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CPU_DT_BIT, /* Descriptor Table */
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/* End of Registers flags */
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CPU_REG_ALL_BIT, /* Select all Registers */
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};
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#define CPU_REG_ALL (~0) /* Select all Registers */
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#define CPU_MC (1 << CPU_MC_BIT)
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#define CPU_MONITOR (1 << CPU_MONITOR_BIT)
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#define CPU_TIME (1 << CPU_TIME_BIT)
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#define CPU_PMC (1 << CPU_PMC_BIT)
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#define CPU_PLATFORM (1 << CPU_PLATFORM_BIT)
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#define CPU_APIC (1 << CPU_APIC_BIT)
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#define CPU_POWERON (1 << CPU_POWERON_BIT)
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#define CPU_CONTROL (1 << CPU_CONTROL_BIT)
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#define CPU_FEATURES (1 << CPU_FEATURES_BIT)
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#define CPU_LBRANCH (1 << CPU_LBRANCH_BIT)
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#define CPU_BIOS (1 << CPU_BIOS_BIT)
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#define CPU_FREQ (1 << CPU_FREQ_BIT)
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#define CPU_MTRR (1 << CPU_MTTR_BIT)
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#define CPU_PERF (1 << CPU_PERF_BIT)
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#define CPU_CACHE (1 << CPU_CACHE_BIT)
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#define CPU_SYSENTER (1 << CPU_SYSENTER_BIT)
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#define CPU_THERM (1 << CPU_THERM_BIT)
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#define CPU_MISC (1 << CPU_MISC_BIT)
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#define CPU_DEBUG (1 << CPU_DEBUG_BIT)
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#define CPU_PAT (1 << CPU_PAT_BIT)
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#define CPU_VMX (1 << CPU_VMX_BIT)
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#define CPU_CALL (1 << CPU_CALL_BIT)
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#define CPU_BASE (1 << CPU_BASE_BIT)
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#define CPU_VER (1 << CPU_VER_BIT)
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#define CPU_CONF (1 << CPU_CONF_BIT)
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#define CPU_SMM (1 << CPU_SMM_BIT)
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#define CPU_SVM (1 << CPU_SVM_BIT)
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#define CPU_OSVM (1 << CPU_OSVM_BIT)
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#define CPU_TSS (1 << CPU_TSS_BIT)
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#define CPU_CR (1 << CPU_CR_BIT)
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#define CPU_DT (1 << CPU_DT_BIT)
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/* Register file flags */
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enum cpu_file_bit {
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CPU_INDEX_BIT, /* index */
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CPU_VALUE_BIT, /* value */
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};
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#define CPU_FILE_VALUE (1 << CPU_VALUE_BIT)
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#define MAX_CPU_FILES 512
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struct cpu_private {
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unsigned cpu;
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unsigned type;
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unsigned reg;
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unsigned file;
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};
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struct cpu_debug_base {
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char *name; /* Register name */
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unsigned flag; /* Register flag */
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unsigned write; /* Register write flag */
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};
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/*
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* Currently it looks similar to cpu_debug_base but once we add more files
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* cpu_file_base will go in different direction
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*/
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struct cpu_file_base {
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char *name; /* Register file name */
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unsigned flag; /* Register file flag */
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unsigned write; /* Register write flag */
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};
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struct cpu_cpuX_base {
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struct dentry *dentry; /* Register dentry */
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int init; /* Register index file */
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};
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struct cpu_debug_range {
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unsigned min; /* Register range min */
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unsigned max; /* Register range max */
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unsigned flag; /* Supported flags */
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};
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#endif /* _ASM_X86_CPU_DEBUG_H */
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