forked from luck/tmp_suning_uos_patched
6fbde6b492
Current Loongson-3 code can share among all Loongson64 processors. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: linux-mips@vger.kernel.org Cc: chenhc@lemote.com Cc: paul.burton@mips.com
163 lines
3.9 KiB
C
163 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <loongson.h>
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#include <irq.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <asm/irq_cpu.h>
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#include <asm/i8259.h>
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#include <asm/mipsregs.h>
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#include "smp.h"
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extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
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unsigned int irq_cpu[16] = {[0 ... 15] = -1};
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unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
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unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;
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int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
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bool force)
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{
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unsigned int cpu;
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struct cpumask new_affinity;
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/* I/O devices are connected on package-0 */
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cpumask_copy(&new_affinity, affinity);
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for_each_cpu(cpu, affinity)
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if (cpu_data[cpu].package > 0)
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cpumask_clear_cpu(cpu, &new_affinity);
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if (cpumask_empty(&new_affinity))
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return -EINVAL;
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cpumask_copy(d->common->affinity, &new_affinity);
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return IRQ_SET_MASK_OK_NOCOPY;
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}
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static void ht_irqdispatch(void)
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{
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unsigned int i, irq;
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struct irq_data *irqd;
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struct cpumask affinity;
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irq = LOONGSON_HT1_INT_VECTOR(0);
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LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
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for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
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if (!(irq & (0x1 << ht_irq[i])))
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continue;
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/* handled by local core */
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if (local_irq & (0x1 << ht_irq[i])) {
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do_IRQ(ht_irq[i]);
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continue;
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}
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irqd = irq_get_irq_data(ht_irq[i]);
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cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
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if (cpumask_empty(&affinity)) {
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do_IRQ(ht_irq[i]);
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continue;
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}
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irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
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if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
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irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
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if (irq_cpu[ht_irq[i]] == 0) {
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do_IRQ(ht_irq[i]);
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continue;
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}
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/* balanced by other cores */
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loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
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}
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}
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#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending;
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pending = read_c0_cause() & read_c0_status() & ST0_IM;
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if (pending & CAUSEF_IP7)
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do_IRQ(LOONGSON_TIMER_IRQ);
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#if defined(CONFIG_SMP)
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if (pending & CAUSEF_IP6)
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loongson3_ipi_interrupt(NULL);
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#endif
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if (pending & CAUSEF_IP3)
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ht_irqdispatch();
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if (pending & CAUSEF_IP2)
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do_IRQ(LOONGSON_UART_IRQ);
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if (pending & UNUSED_IPS) {
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pr_err("%s : spurious interrupt\n", __func__);
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spurious_interrupt();
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}
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}
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static inline void mask_loongson_irq(struct irq_data *d) { }
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static inline void unmask_loongson_irq(struct irq_data *d) { }
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/* For MIPS IRQs which shared by all cores */
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static struct irq_chip loongson_irq_chip = {
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.name = "Loongson",
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.irq_ack = mask_loongson_irq,
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.irq_mask = mask_loongson_irq,
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.irq_mask_ack = mask_loongson_irq,
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.irq_unmask = unmask_loongson_irq,
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.irq_eoi = unmask_loongson_irq,
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};
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void irq_router_init(void)
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{
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int i;
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/* route LPC int to cpu core0 int 0 */
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LOONGSON_INT_ROUTER_LPC =
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LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
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/* route HT1 int0 ~ int7 to cpu core0 INT1*/
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for (i = 0; i < 8; i++)
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LOONGSON_INT_ROUTER_HT1(i) =
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LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
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/* enable HT1 interrupt */
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LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
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/* enable router interrupt intenset */
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LOONGSON_INT_ROUTER_INTENSET =
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LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
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}
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void __init arch_init_irq(void)
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{
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struct irq_chip *chip;
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clear_c0_status(ST0_IM | ST0_BEV);
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irq_router_init();
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mips_cpu_irq_init();
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init_i8259_irqs();
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chip = irq_get_chip(I8259A_IRQ_BASE);
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chip->irq_set_affinity = plat_set_irq_affinity;
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irq_set_chip_and_handler(LOONGSON_UART_IRQ,
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&loongson_irq_chip, handle_percpu_irq);
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irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
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&loongson_irq_chip, handle_percpu_irq);
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set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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void fixup_irqs(void)
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{
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irq_cpu_offline();
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clear_c0_status(ST0_IM);
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}
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#endif
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