forked from luck/tmp_suning_uos_patched
75d67a5490
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of version 2 of the gnu general public license as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa the full gnu general public license is included in this distribution in the file called copying extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 3 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.257093620@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
51 lines
1.2 KiB
C
51 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Intel_SCU 0.2: An Intel SCU IOH Based Watchdog Device
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* for Intel part #(s):
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* - AF82MP20 PCH
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*
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* Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
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*/
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#ifndef __INTEL_SCU_WATCHDOG_H
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#define __INTEL_SCU_WATCHDOG_H
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#define WDT_VER "0.3"
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/* minimum time between interrupts */
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#define MIN_TIME_CYCLE 1
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/* Time from warning to reboot is 2 seconds */
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#define DEFAULT_SOFT_TO_HARD_MARGIN 2
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#define MAX_TIME 170
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#define DEFAULT_TIME 5
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#define MAX_SOFT_TO_HARD_MARGIN (MAX_TIME-MIN_TIME_CYCLE)
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/* Ajustment to clock tick frequency to make timing come out right */
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#define FREQ_ADJUSTMENT 8
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struct intel_scu_watchdog_dev {
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ulong driver_open;
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ulong driver_closed;
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u32 timer_started;
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u32 timer_set;
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u32 threshold;
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u32 soft_threshold;
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u32 __iomem *timer_load_count_addr;
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u32 __iomem *timer_current_value_addr;
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u32 __iomem *timer_control_addr;
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u32 __iomem *timer_clear_interrupt_addr;
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u32 __iomem *timer_interrupt_status_addr;
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struct sfi_timer_table_entry *timer_tbl_ptr;
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struct notifier_block intel_scu_notifier;
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struct miscdevice miscdev;
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};
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extern int sfi_mtimer_num;
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/* extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); */
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#endif /* __INTEL_SCU_WATCHDOG_H */
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