forked from luck/tmp_suning_uos_patched
0d9ea75443
Instead of using the variable mmu_huge_psize to keep track of the huge page size we use an array of MMU_PAGE_* values. For each supported huge page size we need to know the hugepte_shift value and have a pgtable_cache. The hstate or an mmu_huge_psizes index is passed to functions so that they know which huge page size they should use. The hugepage sizes 16M and 64K are setup(if available on the hardware) so that they don't have to be set on the boot cmd line in order to use them. The number of 16G pages have to be specified at boot-time though (e.g. hugepagesz=16G hugepages=5). Signed-off-by: Jon Tollefson <kniht@linux.vnet.ibm.com> Signed-off-by: Nick Piggin <npiggin@suse.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
186 lines
5.0 KiB
C
186 lines
5.0 KiB
C
#ifndef _ASM_POWERPC_PAGE_64_H
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#define _ASM_POWERPC_PAGE_64_H
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/*
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* Copyright (C) 2001 PPC64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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/*
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* We always define HW_PAGE_SHIFT to 12 as use of 64K pages remains Linux
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* specific, every notion of page number shared with the firmware, TCEs,
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* iommu, etc... still uses a page size of 4K.
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*/
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#define HW_PAGE_SHIFT 12
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#define HW_PAGE_SIZE (ASM_CONST(1) << HW_PAGE_SHIFT)
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#define HW_PAGE_MASK (~(HW_PAGE_SIZE-1))
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/*
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* PAGE_FACTOR is the number of bits factor between PAGE_SHIFT and
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* HW_PAGE_SHIFT, that is 4K pages.
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*/
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#define PAGE_FACTOR (PAGE_SHIFT - HW_PAGE_SHIFT)
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/* Segment size; normal 256M segments */
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#define SID_SHIFT 28
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#define SID_MASK ASM_CONST(0xfffffffff)
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#define ESID_MASK 0xfffffffff0000000UL
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#define GET_ESID(x) (((x) >> SID_SHIFT) & SID_MASK)
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/* 1T segments */
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#define SID_SHIFT_1T 40
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#define SID_MASK_1T 0xffffffUL
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#define ESID_MASK_1T 0xffffff0000000000UL
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#define GET_ESID_1T(x) (((x) >> SID_SHIFT_1T) & SID_MASK_1T)
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#ifndef __ASSEMBLY__
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#include <asm/cache.h>
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typedef unsigned long pte_basic_t;
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static __inline__ void clear_page(void *addr)
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{
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unsigned long lines, line_size;
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line_size = ppc64_caches.dline_size;
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lines = ppc64_caches.dlines_per_page;
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__asm__ __volatile__(
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"mtctr %1 # clear_page\n\
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1: dcbz 0,%0\n\
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add %0,%0,%3\n\
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bdnz+ 1b"
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: "=r" (addr)
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: "r" (lines), "0" (addr), "r" (line_size)
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: "ctr", "memory");
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}
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extern void copy_4K_page(void *to, void *from);
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#ifdef CONFIG_PPC_64K_PAGES
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static inline void copy_page(void *to, void *from)
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{
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unsigned int i;
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for (i=0; i < (1 << (PAGE_SHIFT - 12)); i++) {
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copy_4K_page(to, from);
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to += 4096;
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from += 4096;
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}
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}
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#else /* CONFIG_PPC_64K_PAGES */
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static inline void copy_page(void *to, void *from)
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{
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copy_4K_page(to, from);
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}
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#endif /* CONFIG_PPC_64K_PAGES */
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/* Log 2 of page table size */
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extern u64 ppc64_pft_size;
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/* Large pages size */
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#ifdef CONFIG_HUGETLB_PAGE
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extern unsigned int HPAGE_SHIFT;
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#else
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#define HPAGE_SHIFT PAGE_SHIFT
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#endif
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#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
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#define HPAGE_MASK (~(HPAGE_SIZE - 1))
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#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
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#define HUGE_MAX_HSTATE 3
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_PPC_MM_SLICES
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#define SLICE_LOW_SHIFT 28
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#define SLICE_HIGH_SHIFT 40
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#define SLICE_LOW_TOP (0x100000000ul)
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#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
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#define SLICE_NUM_HIGH (PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
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#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
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#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
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#ifndef __ASSEMBLY__
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struct slice_mask {
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u16 low_slices;
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u16 high_slices;
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};
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struct mm_struct;
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extern unsigned long slice_get_unmapped_area(unsigned long addr,
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unsigned long len,
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unsigned long flags,
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unsigned int psize,
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int topdown,
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int use_cache);
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extern unsigned int get_slice_psize(struct mm_struct *mm,
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unsigned long addr);
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extern void slice_init_context(struct mm_struct *mm, unsigned int psize);
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extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
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extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
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unsigned long len, unsigned int psize);
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#define slice_mm_new_context(mm) ((mm)->context.id == 0)
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#endif /* __ASSEMBLY__ */
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#else
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#define slice_init()
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#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
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#define slice_set_user_psize(mm, psize) \
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do { \
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(mm)->context.user_psize = (psize); \
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(mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
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} while (0)
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#define slice_set_range_psize(mm, start, len, psize) \
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slice_set_user_psize((mm), (psize))
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#define slice_mm_new_context(mm) 1
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#endif /* CONFIG_PPC_MM_SLICES */
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#ifdef CONFIG_HUGETLB_PAGE
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#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
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#endif /* !CONFIG_HUGETLB_PAGE */
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#ifdef MODULE
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#define __page_aligned __attribute__((__aligned__(PAGE_SIZE)))
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#else
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#define __page_aligned \
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__attribute__((__aligned__(PAGE_SIZE), \
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__section__(".data.page_aligned")))
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#endif
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#define VM_DATA_DEFAULT_FLAGS \
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(test_thread_flag(TIF_32BIT) ? \
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VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
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/*
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* This is the default if a program doesn't have a PT_GNU_STACK
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* program header entry. The PPC64 ELF ABI has a non executable stack
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* stack by default, so in the absense of a PT_GNU_STACK program header
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* we turn execute permission off.
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*/
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#define VM_STACK_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#define VM_STACK_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#define VM_STACK_DEFAULT_FLAGS \
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(test_thread_flag(TIF_32BIT) ? \
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VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
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#include <asm-generic/page.h>
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#endif /* _ASM_POWERPC_PAGE_64_H */
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