forked from luck/tmp_suning_uos_patched
d3cb487149
Several counters already have the need to use 64 atomic variables on 64 bit platforms (see mm_counter_t in sched.h). We have to do ugly ifdefs to fall back to 32 bit atomic on 32 bit platforms. The VM statistics patch that I am working on will also make more extensive use of atomic64. This patch introduces a new type atomic_long_t by providing definitions in asm-generic/atomic.h that works similar to the c "long" type. Its 32 bits on 32 bit platforms and 64 bits on 64 bit platforms. Also cleans up the determination of the mm_counter_t in sched.h. Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
131 lines
2.9 KiB
C
131 lines
2.9 KiB
C
/*
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* include/asm-v850/atomic.h -- Atomic operations
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*
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* Copyright (C) 2001,02 NEC Corporation
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* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_ATOMIC_H__
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#define __V850_ATOMIC_H__
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#include <linux/config.h>
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#include <asm/system.h>
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#ifdef CONFIG_SMP
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#error SMP not supported
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#endif
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typedef struct { int counter; } atomic_t;
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#define ATOMIC_INIT(i) { (i) }
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#ifdef __KERNEL__
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v,i) (((v)->counter) = (i))
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static inline int atomic_add_return (int i, volatile atomic_t *v)
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{
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unsigned long flags;
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int res;
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local_irq_save (flags);
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res = v->counter + i;
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v->counter = res;
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local_irq_restore (flags);
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return res;
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}
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static __inline__ int atomic_sub_return (int i, volatile atomic_t *v)
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{
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unsigned long flags;
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int res;
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local_irq_save (flags);
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res = v->counter - i;
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v->counter = res;
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local_irq_restore (flags);
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return res;
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}
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static __inline__ void atomic_clear_mask (unsigned long mask, unsigned long *addr)
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{
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unsigned long flags;
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local_irq_save (flags);
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*addr &= ~mask;
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local_irq_restore (flags);
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}
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#endif
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#define atomic_add(i, v) atomic_add_return ((i), (v))
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#define atomic_sub(i, v) atomic_sub_return ((i), (v))
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#define atomic_dec_return(v) atomic_sub_return (1, (v))
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#define atomic_inc_return(v) atomic_add_return (1, (v))
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#define atomic_inc(v) atomic_inc_return (v)
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#define atomic_dec(v) atomic_dec_return (v)
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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#define atomic_sub_and_test(i,v) (atomic_sub_return ((i), (v)) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return (1, (v)) == 0)
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#define atomic_add_negative(i,v) (atomic_add_return ((i), (v)) < 0)
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static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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int ret;
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unsigned long flags;
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local_irq_save(flags);
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ret = v->counter;
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if (likely(ret == old))
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v->counter = new;
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local_irq_restore(flags);
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return ret;
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}
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static inline int atomic_add_unless(atomic_t *v, int a, int u)
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{
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int ret;
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unsigned long flags;
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local_irq_save(flags);
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ret = v->counter;
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if (ret != u)
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v->counter += a;
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local_irq_restore(flags);
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return ret != u;
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}
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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/* Atomic operations are already serializing on ARM */
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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#include <asm-generic/atomic.h>
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#endif /* __V850_ATOMIC_H__ */
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