forked from luck/tmp_suning_uos_patched
26b7a78c55
This converts the lazy dcache handling to the model described in Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a bonus, this slightly cuts down on the cache flushing frequency. With that and the PTEA handling out of the way, the update_mmu_cache() implementations can be consolidated, and we no longer have to worry about which configuration the cache is in for the SH7705 case. And finally, explicitly disable the lazy writeback on SMP (SH-4A). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
111 lines
2.5 KiB
C
111 lines
2.5 KiB
C
/*
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* arch/sh/mm/pg-sh7705.c
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka
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* Copyright (C) 2004 Alex Song
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/threads.h>
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#include <asm/addrspace.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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static inline void __flush_purge_virtual_region(void *p1, void *virt, int size)
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{
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unsigned long v;
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unsigned long begin, end;
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unsigned long p1_begin;
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begin = L1_CACHE_ALIGN((unsigned long)virt);
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end = L1_CACHE_ALIGN((unsigned long)virt + size);
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p1_begin = (unsigned long)p1 & ~(L1_CACHE_BYTES - 1);
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/* do this the slow way as we may not have TLB entries
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* for virt yet. */
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for (v = begin; v < end; v += L1_CACHE_BYTES) {
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unsigned long p;
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unsigned long ways, addr;
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p = __pa(p1_begin);
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ways = cpu_data->dcache.ways;
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addr = CACHE_OC_ADDRESS_ARRAY;
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do {
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unsigned long data;
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addr |= (v & cpu_data->dcache.entry_mask);
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data = ctrl_inl(addr);
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if ((data & CACHE_PHYSADDR_MASK) ==
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(p & CACHE_PHYSADDR_MASK)) {
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data &= ~(SH_CACHE_UPDATED|SH_CACHE_VALID);
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ctrl_outl(data, addr);
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}
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addr += cpu_data->dcache.way_incr;
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} while (--ways);
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p1_begin += L1_CACHE_BYTES;
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}
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}
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/*
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* clear_user_page
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* @to: P1 address
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* @address: U0 address to be mapped
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*/
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void clear_user_page(void *to, unsigned long address, struct page *pg)
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{
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struct page *page = virt_to_page(to);
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if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) {
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clear_page(to);
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__flush_wback_region(to, PAGE_SIZE);
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} else {
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__flush_purge_virtual_region(to,
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(void *)(address & 0xfffff000),
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PAGE_SIZE);
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clear_page(to);
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__flush_wback_region(to, PAGE_SIZE);
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}
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}
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/*
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* copy_user_page
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* @to: P1 address
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* @from: P1 address
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* @address: U0 address to be mapped
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*/
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void copy_user_page(void *to, void *from, unsigned long address,
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struct page *pg)
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{
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struct page *page = virt_to_page(to);
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if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) {
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copy_page(to, from);
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__flush_wback_region(to, PAGE_SIZE);
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} else {
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__flush_purge_virtual_region(to,
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(void *)(address & 0xfffff000),
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PAGE_SIZE);
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copy_page(to, from);
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__flush_wback_region(to, PAGE_SIZE);
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}
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}
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