forked from luck/tmp_suning_uos_patched
d532f3d267
Original patch by Ralf Baechle and removed by Harold Koerfgen with commit f67e4ffc79905482c3b9b8c8dd65197bac7eb508. This allows for more generic kernels since the size of the ASID and corresponding masks can be determined at run-time. This patch is also required for the new Aptiv cores and has been tested on Malta and Malta Aptiv platforms. [ralf@linux-mips.org: Added relevant part of fix https://patchwork.linux-mips.org/patch/5213/] Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
65 lines
1.5 KiB
C
65 lines
1.5 KiB
C
/*
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* Dump R3000 TLB for debugging purposes.
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*
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* Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
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* Copyright (C) 1999 by Silicon Graphics, Inc.
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* Copyright (C) 1999 by Harald Koerfgen
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <asm/mipsregs.h>
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#include <asm/mmu_context.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/tlbdebug.h>
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extern int r3k_have_wired_reg; /* defined in tlb-r3k.c */
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static void dump_tlb(int first, int last)
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{
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int i;
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unsigned int asid;
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unsigned long entryhi, entrylo0;
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asid = ASID_MASK(read_c0_entryhi());
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for (i = first; i <= last; i++) {
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write_c0_index(i<<8);
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__asm__ __volatile__(
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".set\tnoreorder\n\t"
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"tlbr\n\t"
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"nop\n\t"
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".set\treorder");
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entryhi = read_c0_entryhi();
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entrylo0 = read_c0_entrylo0();
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/* Unused entries have a virtual address of KSEG0. */
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if ((entryhi & 0xffffe000) != 0x80000000
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&& (ASID_MASK(entryhi) == asid)) {
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/*
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* Only print entries in use
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*/
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printk("Index: %2d ", i);
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printk("va=%08lx asid=%08lx"
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" [pa=%06lx n=%d d=%d v=%d g=%d]",
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(entryhi & 0xffffe000),
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ASID_MASK(entryhi),
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entrylo0 & PAGE_MASK,
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(entrylo0 & (1 << 11)) ? 1 : 0,
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(entrylo0 & (1 << 10)) ? 1 : 0,
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(entrylo0 & (1 << 9)) ? 1 : 0,
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(entrylo0 & (1 << 8)) ? 1 : 0);
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}
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}
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printk("\n");
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write_c0_entryhi(asid);
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}
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void dump_tlb_all(void)
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{
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dump_tlb(0, current_cpu_data.tlbsize - 1);
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}
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