forked from luck/tmp_suning_uos_patched
b36ca91e1d
This patch adds the functions to allocate and deallocate the command buffer for one IOMMU in the system. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Cc: iommu@lists.linux-foundation.org Cc: bhavna.sarathy@amd.com Cc: Sebastian.Biemueller@amd.com Cc: robert.richter@amd.com Cc: joro@8bytes.org Signed-off-by: Ingo Molnar <mingo@elte.hu>
311 lines
7.4 KiB
C
311 lines
7.4 KiB
C
/*
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* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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* Leo Duran <leo.duran@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <linux/gfp.h>
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#include <linux/list.h>
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#include <asm/pci-direct.h>
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#include <asm/amd_iommu_types.h>
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#include <asm/gart.h>
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/*
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* definitions for the ACPI scanning code
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*/
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#define UPDATE_LAST_BDF(x) do {\
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if ((x) > amd_iommu_last_bdf) \
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amd_iommu_last_bdf = (x); \
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} while (0);
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#define DEVID(bus, devfn) (((bus) << 8) | (devfn))
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#define PCI_BUS(x) (((x) >> 8) & 0xff)
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#define IVRS_HEADER_LENGTH 48
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#define TBL_SIZE(x) (1 << (PAGE_SHIFT + get_order(amd_iommu_last_bdf * (x))))
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#define ACPI_IVHD_TYPE 0x10
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#define ACPI_IVMD_TYPE_ALL 0x20
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#define ACPI_IVMD_TYPE 0x21
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#define ACPI_IVMD_TYPE_RANGE 0x22
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#define IVHD_DEV_ALL 0x01
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#define IVHD_DEV_SELECT 0x02
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#define IVHD_DEV_SELECT_RANGE_START 0x03
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#define IVHD_DEV_RANGE_END 0x04
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#define IVHD_DEV_ALIAS 0x42
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#define IVHD_DEV_ALIAS_RANGE 0x43
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#define IVHD_DEV_EXT_SELECT 0x46
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#define IVHD_DEV_EXT_SELECT_RANGE 0x47
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#define IVHD_FLAG_HT_TUN_EN 0x00
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#define IVHD_FLAG_PASSPW_EN 0x01
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#define IVHD_FLAG_RESPASSPW_EN 0x02
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#define IVHD_FLAG_ISOC_EN 0x03
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#define IVMD_FLAG_EXCL_RANGE 0x08
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#define IVMD_FLAG_UNITY_MAP 0x01
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#define ACPI_DEVFLAG_INITPASS 0x01
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#define ACPI_DEVFLAG_EXTINT 0x02
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#define ACPI_DEVFLAG_NMI 0x04
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#define ACPI_DEVFLAG_SYSMGT1 0x10
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#define ACPI_DEVFLAG_SYSMGT2 0x20
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#define ACPI_DEVFLAG_LINT0 0x40
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#define ACPI_DEVFLAG_LINT1 0x80
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#define ACPI_DEVFLAG_ATSDIS 0x10000000
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struct ivhd_header {
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u8 type;
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u8 flags;
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u16 length;
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u16 devid;
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u16 cap_ptr;
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u64 mmio_phys;
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u16 pci_seg;
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u16 info;
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u32 reserved;
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} __attribute__((packed));
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struct ivhd_entry {
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u8 type;
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u16 devid;
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u8 flags;
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u32 ext;
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} __attribute__((packed));
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struct ivmd_header {
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u8 type;
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u8 flags;
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u16 length;
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u16 devid;
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u16 aux;
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u64 resv;
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u64 range_start;
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u64 range_length;
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} __attribute__((packed));
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static int __initdata amd_iommu_disable;
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u16 amd_iommu_last_bdf;
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struct list_head amd_iommu_unity_map;
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unsigned amd_iommu_aperture_order = 26;
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int amd_iommu_isolate;
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struct list_head amd_iommu_list;
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struct dev_table_entry *amd_iommu_dev_table;
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u16 *amd_iommu_alias_table;
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struct amd_iommu **amd_iommu_rlookup_table;
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struct protection_domain **amd_iommu_pd_table;
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unsigned long *amd_iommu_pd_alloc_bitmap;
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static u32 dev_table_size;
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static u32 alias_table_size;
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static u32 rlookup_table_size;
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static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
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{
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u64 start = iommu->exclusion_start & PAGE_MASK;
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u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
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u64 entry;
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if (!iommu->exclusion_start)
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return;
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entry = start | MMIO_EXCL_ENABLE_MASK;
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memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
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&entry, sizeof(entry));
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entry = limit;
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memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
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&entry, sizeof(entry));
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}
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static void __init iommu_set_device_table(struct amd_iommu *iommu)
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{
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u32 entry;
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BUG_ON(iommu->mmio_base == NULL);
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entry = virt_to_phys(amd_iommu_dev_table);
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entry |= (dev_table_size >> 12) - 1;
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memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
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&entry, sizeof(entry));
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}
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static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
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{
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u32 ctrl;
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ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
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ctrl |= (1 << bit);
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writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
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}
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static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
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{
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u32 ctrl;
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ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
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ctrl &= ~(1 << bit);
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writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
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}
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void __init iommu_enable(struct amd_iommu *iommu)
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{
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u32 ctrl;
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printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at ");
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print_devid(iommu->devid, 0);
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printk(" cap 0x%hx\n", iommu->cap_ptr);
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iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
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ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
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}
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static u8 * __init iommu_map_mmio_space(u64 address)
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{
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u8 *ret;
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if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
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return NULL;
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ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
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if (ret != NULL)
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return ret;
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release_mem_region(address, MMIO_REGION_LENGTH);
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return NULL;
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}
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static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
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{
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if (iommu->mmio_base)
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iounmap(iommu->mmio_base);
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release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
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}
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static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
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{
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u32 cap;
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cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
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UPDATE_LAST_BDF(DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
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return 0;
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}
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static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
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{
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u8 *p = (void *)h, *end = (void *)h;
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struct ivhd_entry *dev;
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p += sizeof(*h);
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end += h->length;
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find_last_devid_on_pci(PCI_BUS(h->devid),
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PCI_SLOT(h->devid),
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PCI_FUNC(h->devid),
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h->cap_ptr);
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while (p < end) {
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dev = (struct ivhd_entry *)p;
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switch (dev->type) {
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case IVHD_DEV_SELECT:
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case IVHD_DEV_RANGE_END:
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case IVHD_DEV_ALIAS:
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case IVHD_DEV_EXT_SELECT:
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UPDATE_LAST_BDF(dev->devid);
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break;
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default:
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break;
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}
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p += 0x04 << (*p >> 6);
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}
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WARN_ON(p != end);
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return 0;
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}
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static int __init find_last_devid_acpi(struct acpi_table_header *table)
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{
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int i;
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u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
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struct ivhd_header *h;
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/*
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* Validate checksum here so we don't need to do it when
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* we actually parse the table
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*/
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for (i = 0; i < table->length; ++i)
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checksum += p[i];
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if (checksum != 0)
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/* ACPI table corrupt */
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return -ENODEV;
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p += IVRS_HEADER_LENGTH;
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end += table->length;
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while (p < end) {
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h = (struct ivhd_header *)p;
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switch (h->type) {
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case ACPI_IVHD_TYPE:
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find_last_devid_from_ivhd(h);
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break;
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default:
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break;
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}
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p += h->length;
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}
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WARN_ON(p != end);
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return 0;
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}
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static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
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{
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u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL,
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get_order(CMD_BUFFER_SIZE));
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u64 entry = 0;
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if (cmd_buf == NULL)
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return NULL;
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iommu->cmd_buf_size = CMD_BUFFER_SIZE;
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memset(cmd_buf, 0, CMD_BUFFER_SIZE);
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entry = (u64)virt_to_phys(cmd_buf);
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entry |= MMIO_CMD_SIZE_512;
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memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
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&entry, sizeof(entry));
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iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
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return cmd_buf;
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}
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static void __init free_command_buffer(struct amd_iommu *iommu)
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{
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if (iommu->cmd_buf)
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free_pages((unsigned long)iommu->cmd_buf,
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get_order(CMD_BUFFER_SIZE));
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}
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