forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
721 lines
18 KiB
ArmAsm
721 lines
18 KiB
ArmAsm
/* break.S: Break interrupt handling (kept separate from entry.S)
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*
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* Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/sys.h>
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <asm/setup.h>
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#include <asm/segment.h>
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#include <asm/ptrace.h>
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#include <asm/spr-regs.h>
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#include <asm/errno.h>
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#
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# the break handler has its own stack
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#
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.section .bss.stack
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.globl __break_user_context
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.balign 8192
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__break_stack:
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.space (8192 - (USER_CONTEXT_SIZE + REG__DEBUG_XTRA)) & ~7
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__break_stack_tos:
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.space REG__DEBUG_XTRA
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__break_user_context:
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.space USER_CONTEXT_SIZE
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#
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# miscellaneous variables
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#
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.section .bss
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#ifdef CONFIG_MMU
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.globl __break_tlb_miss_real_return_info
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__break_tlb_miss_real_return_info:
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.balign 8
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.space 2*4 /* saved PCSR, PSR for TLB-miss handler fixup */
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#endif
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__break_trace_through_exceptions:
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.space 4
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#define CS2_ECS1 0xe1200000
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#define CS2_USERLED 0x4
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.macro LEDS val,reg
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# sethi.p %hi(CS2_ECS1+CS2_USERLED),gr30
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# setlo %lo(CS2_ECS1+CS2_USERLED),gr30
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# setlos #~\val,\reg
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# st \reg,@(gr30,gr0)
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# setlos #0x5555,\reg
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# sethi.p %hi(0xffc00100),gr30
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# setlo %lo(0xffc00100),gr30
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# sth \reg,@(gr30,gr0)
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# membar
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.endm
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###############################################################################
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#
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# entry point for Break Exceptions/Interrupts
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#
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###############################################################################
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.text
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.balign 4
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.globl __entry_break
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__entry_break:
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#ifdef CONFIG_MMU
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movgs gr31,scr3
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#endif
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LEDS 0x1001,gr31
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sethi.p %hi(__break_user_context),gr31
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setlo %lo(__break_user_context),gr31
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stdi gr2,@(gr31,#REG_GR(2))
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movsg ccr,gr3
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sti gr3,@(gr31,#REG_CCR)
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# catch the return from a TLB-miss handler that had single-step disabled
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# traps will be enabled, so we have to do this now
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#ifdef CONFIG_MMU
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movsg bpcsr,gr3
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sethi.p %hi(__break_tlb_miss_return_breaks_here),gr2
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setlo %lo(__break_tlb_miss_return_breaks_here),gr2
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subcc gr2,gr3,gr0,icc0
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beq icc0,#2,__break_return_singlestep_tlbmiss
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#endif
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# determine whether we have stepped through into an exception
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# - we need to take special action to suspend h/w single stepping if we've done
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# that, so that the gdbstub doesn't get bogged down endlessly stepping through
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# external interrupt handling
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movsg bpsr,gr3
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andicc gr3,#BPSR_BET,gr0,icc0
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bne icc0,#2,__break_maybe_userspace /* jump if PSR.ET was 1 */
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LEDS 0x1003,gr2
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movsg brr,gr3
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andicc gr3,#BRR_ST,gr0,icc0
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andicc.p gr3,#BRR_SB,gr0,icc1
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bne icc0,#2,__break_step /* jump if single-step caused break */
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beq icc1,#2,__break_continue /* jump if BREAK didn't cause break */
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LEDS 0x1007,gr2
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# handle special breaks
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movsg bpcsr,gr3
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sethi.p %hi(__entry_return_singlestep_breaks_here),gr2
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setlo %lo(__entry_return_singlestep_breaks_here),gr2
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subcc gr2,gr3,gr0,icc0
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beq icc0,#2,__break_return_singlestep
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bra __break_continue
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###############################################################################
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#
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# handle BREAK instruction in kernel-mode exception epilogue
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#
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###############################################################################
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__break_return_singlestep:
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LEDS 0x100f,gr2
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# special break insn requests single-stepping to be turned back on
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# HERE RETT
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# PSR.ET 0 0
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# PSR.PS old PSR.S ?
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# PSR.S 1 1
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# BPSR.ET 0 1 (can't have caused orig excep otherwise)
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# BPSR.BS 1 old PSR.S
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movsg dcr,gr2
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sethi.p %hi(DCR_SE),gr3
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setlo %lo(DCR_SE),gr3
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or gr2,gr3,gr2
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movgs gr2,dcr
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movsg psr,gr2
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andi gr2,#PSR_PS,gr2
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slli gr2,#11,gr2 /* PSR.PS -> BPSR.BS */
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ori gr2,#BPSR_BET,gr2 /* 1 -> BPSR.BET */
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movgs gr2,bpsr
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# return to the invoker of the original kernel exception
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movsg pcsr,gr2
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movgs gr2,bpcsr
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LEDS 0x101f,gr2
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ldi @(gr31,#REG_CCR),gr3
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movgs gr3,ccr
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lddi.p @(gr31,#REG_GR(2)),gr2
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xor gr31,gr31,gr31
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movgs gr0,brr
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#ifdef CONFIG_MMU
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movsg scr3,gr31
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#endif
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rett #1
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###############################################################################
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#
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# handle BREAK instruction in TLB-miss handler return path
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#
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###############################################################################
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#ifdef CONFIG_MMU
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__break_return_singlestep_tlbmiss:
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LEDS 0x1100,gr2
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sethi.p %hi(__break_tlb_miss_real_return_info),gr3
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setlo %lo(__break_tlb_miss_real_return_info),gr3
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lddi @(gr3,#0),gr2
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movgs gr2,pcsr
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movgs gr3,psr
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bra __break_return_singlestep
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#endif
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###############################################################################
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#
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# handle single stepping into an exception prologue from kernel mode
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# - we try and catch it whilst it is still in the main vector table
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# - if we catch it there, we have to jump to the fixup handler
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# - there is a fixup table that has a pointer for every 16b slot in the trap
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# table
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#
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###############################################################################
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__break_step:
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LEDS 0x2003,gr2
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# external interrupts seem to escape from the trap table before single
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# step catches up with them
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movsg bpcsr,gr2
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sethi.p %hi(__entry_kernel_external_interrupt),gr3
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setlo %lo(__entry_kernel_external_interrupt),gr3
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subcc gr2,gr3,gr0,icc0
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beq icc0,#2,__break_step_kernel_external_interrupt
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sethi.p %hi(__entry_uspace_external_interrupt),gr3
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setlo %lo(__entry_uspace_external_interrupt),gr3
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subcc gr2,gr3,gr0,icc0
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beq icc0,#2,__break_step_uspace_external_interrupt
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LEDS 0x2007,gr2
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# the two main vector tables are adjacent on one 8Kb slab
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movsg bpcsr,gr2
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setlos #0xffffe000,gr3
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and gr2,gr3,gr2
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sethi.p %hi(__trap_tables),gr3
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setlo %lo(__trap_tables),gr3
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subcc gr2,gr3,gr0,icc0
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bne icc0,#2,__break_continue
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LEDS 0x200f,gr2
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# skip workaround if so requested by GDB
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sethi.p %hi(__break_trace_through_exceptions),gr3
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setlo %lo(__break_trace_through_exceptions),gr3
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ld @(gr3,gr0),gr3
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subcc gr3,gr0,gr0,icc0
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bne icc0,#0,__break_continue
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LEDS 0x201f,gr2
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# access the fixup table - there's a 1:1 mapping between the slots in the trap tables and
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# the slots in the trap fixup tables allowing us to simply divide the offset into the
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# former by 4 to access the latter
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sethi.p %hi(__trap_tables),gr3
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setlo %lo(__trap_tables),gr3
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movsg bpcsr,gr2
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sub gr2,gr3,gr2
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srli.p gr2,#2,gr2
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sethi %hi(__trap_fixup_tables),gr3
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setlo.p %lo(__trap_fixup_tables),gr3
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andi gr2,#~3,gr2
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ld @(gr2,gr3),gr2
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jmpil @(gr2,#0)
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# step through an internal exception from kernel mode
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.globl __break_step_kernel_softprog_interrupt
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__break_step_kernel_softprog_interrupt:
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sethi.p %hi(__entry_kernel_softprog_interrupt_reentry),gr3
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setlo %lo(__entry_kernel_softprog_interrupt_reentry),gr3
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bra __break_return_as_kernel_prologue
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# step through an external interrupt from kernel mode
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.globl __break_step_kernel_external_interrupt
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__break_step_kernel_external_interrupt:
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sethi.p %hi(__entry_kernel_external_interrupt_reentry),gr3
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setlo %lo(__entry_kernel_external_interrupt_reentry),gr3
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__break_return_as_kernel_prologue:
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LEDS 0x203f,gr2
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movgs gr3,bpcsr
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# do the bit we had to skip
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#ifdef CONFIG_MMU
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movsg ear0,gr2 /* EAR0 can get clobbered by gdb-stub (ICI/ICEI) */
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movgs gr2,scr2
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#endif
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or.p sp,gr0,gr2 /* set up the stack pointer */
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subi sp,#REG__END,sp
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sti.p gr2,@(sp,#REG_SP)
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setlos #REG__STATUS_STEP,gr2
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sti gr2,@(sp,#REG__STATUS) /* record single step status */
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# cancel single-stepping mode
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movsg dcr,gr2
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sethi.p %hi(~DCR_SE),gr3
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setlo %lo(~DCR_SE),gr3
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and gr2,gr3,gr2
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movgs gr2,dcr
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LEDS 0x207f,gr2
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ldi @(gr31,#REG_CCR),gr3
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movgs gr3,ccr
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lddi.p @(gr31,#REG_GR(2)),gr2
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xor gr31,gr31,gr31
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movgs gr0,brr
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#ifdef CONFIG_MMU
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movsg scr3,gr31
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#endif
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rett #1
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# step through an internal exception from uspace mode
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.globl __break_step_uspace_softprog_interrupt
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__break_step_uspace_softprog_interrupt:
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sethi.p %hi(__entry_uspace_softprog_interrupt_reentry),gr3
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setlo %lo(__entry_uspace_softprog_interrupt_reentry),gr3
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bra __break_return_as_uspace_prologue
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# step through an external interrupt from kernel mode
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.globl __break_step_uspace_external_interrupt
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__break_step_uspace_external_interrupt:
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sethi.p %hi(__entry_uspace_external_interrupt_reentry),gr3
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setlo %lo(__entry_uspace_external_interrupt_reentry),gr3
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__break_return_as_uspace_prologue:
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LEDS 0x20ff,gr2
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movgs gr3,bpcsr
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# do the bit we had to skip
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sethi.p %hi(__kernel_frame0_ptr),gr28
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setlo %lo(__kernel_frame0_ptr),gr28
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ldi.p @(gr28,#0),gr28
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setlos #REG__STATUS_STEP,gr2
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sti gr2,@(gr28,#REG__STATUS) /* record single step status */
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# cancel single-stepping mode
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movsg dcr,gr2
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sethi.p %hi(~DCR_SE),gr3
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setlo %lo(~DCR_SE),gr3
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and gr2,gr3,gr2
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movgs gr2,dcr
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LEDS 0x20fe,gr2
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ldi @(gr31,#REG_CCR),gr3
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movgs gr3,ccr
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lddi.p @(gr31,#REG_GR(2)),gr2
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xor gr31,gr31,gr31
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movgs gr0,brr
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#ifdef CONFIG_MMU
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movsg scr3,gr31
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#endif
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rett #1
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#ifdef CONFIG_MMU
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# step through an ITLB-miss handler from user mode
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.globl __break_user_insn_tlb_miss
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__break_user_insn_tlb_miss:
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# we'll want to try the trap stub again
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sethi.p %hi(__trap_user_insn_tlb_miss),gr2
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setlo %lo(__trap_user_insn_tlb_miss),gr2
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movgs gr2,bpcsr
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__break_tlb_miss_common:
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LEDS 0x2101,gr2
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# cancel single-stepping mode
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movsg dcr,gr2
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sethi.p %hi(~DCR_SE),gr3
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setlo %lo(~DCR_SE),gr3
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and gr2,gr3,gr2
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movgs gr2,dcr
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# we'll swap the real return address for one with a BREAK insn so that we can re-enable
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# single stepping on return
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movsg pcsr,gr2
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sethi.p %hi(__break_tlb_miss_real_return_info),gr3
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setlo %lo(__break_tlb_miss_real_return_info),gr3
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sti gr2,@(gr3,#0)
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sethi.p %hi(__break_tlb_miss_return_break),gr2
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setlo %lo(__break_tlb_miss_return_break),gr2
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movgs gr2,pcsr
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# we also have to fudge PSR because the return BREAK is in kernel space and we want
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# to get a BREAK fault not an access violation should the return be to userspace
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movsg psr,gr2
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sti.p gr2,@(gr3,#4)
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ori gr2,#PSR_PS,gr2
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movgs gr2,psr
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LEDS 0x2102,gr2
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ldi @(gr31,#REG_CCR),gr3
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movgs gr3,ccr
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lddi @(gr31,#REG_GR(2)),gr2
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movsg scr3,gr31
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movgs gr0,brr
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rett #1
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# step through a DTLB-miss handler from user mode
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.globl __break_user_data_tlb_miss
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__break_user_data_tlb_miss:
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# we'll want to try the trap stub again
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sethi.p %hi(__trap_user_data_tlb_miss),gr2
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setlo %lo(__trap_user_data_tlb_miss),gr2
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movgs gr2,bpcsr
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bra __break_tlb_miss_common
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# step through an ITLB-miss handler from kernel mode
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.globl __break_kernel_insn_tlb_miss
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__break_kernel_insn_tlb_miss:
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# we'll want to try the trap stub again
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sethi.p %hi(__trap_kernel_insn_tlb_miss),gr2
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setlo %lo(__trap_kernel_insn_tlb_miss),gr2
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movgs gr2,bpcsr
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bra __break_tlb_miss_common
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# step through a DTLB-miss handler from kernel mode
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.globl __break_kernel_data_tlb_miss
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__break_kernel_data_tlb_miss:
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# we'll want to try the trap stub again
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sethi.p %hi(__trap_kernel_data_tlb_miss),gr2
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setlo %lo(__trap_kernel_data_tlb_miss),gr2
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movgs gr2,bpcsr
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bra __break_tlb_miss_common
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#endif
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###############################################################################
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#
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# handle debug events originating with userspace
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#
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###############################################################################
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__break_maybe_userspace:
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LEDS 0x3003,gr2
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setlos #BPSR_BS,gr2
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andcc gr3,gr2,gr0,icc0
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bne icc0,#0,__break_continue /* skip if PSR.S was 1 */
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movsg brr,gr2
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andicc gr2,#BRR_ST|BRR_SB,gr0,icc0
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beq icc0,#0,__break_continue /* jump if not BREAK or single-step */
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LEDS 0x3007,gr2
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# do the first part of the exception prologue here
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sethi.p %hi(__kernel_frame0_ptr),gr28
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setlo %lo(__kernel_frame0_ptr),gr28
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ldi @(gr28,#0),gr28
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andi gr28,#~7,gr28
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# set up the kernel stack pointer
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sti sp ,@(gr28,#REG_SP)
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ori gr28,0,sp
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sti gr0 ,@(gr28,#REG_GR(28))
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stdi gr20,@(gr28,#REG_GR(20))
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stdi gr22,@(gr28,#REG_GR(22))
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movsg tbr,gr20
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movsg bpcsr,gr21
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movsg psr,gr22
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# determine the exception type and cancel single-stepping mode
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or gr0,gr0,gr23
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movsg dcr,gr2
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sethi.p %hi(DCR_SE),gr3
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setlo %lo(DCR_SE),gr3
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andcc gr2,gr3,gr0,icc0
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beq icc0,#0,__break_no_user_sstep /* must have been a BREAK insn */
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not gr3,gr3
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and gr2,gr3,gr2
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movgs gr2,dcr
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ori gr23,#REG__STATUS_STEP,gr23
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__break_no_user_sstep:
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LEDS 0x300f,gr2
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movsg brr,gr2
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andi gr2,#BRR_ST|BRR_SB,gr2
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slli gr2,#1,gr2
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or gr23,gr2,gr23
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sti.p gr23,@(gr28,#REG__STATUS) /* record single step status */
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# adjust the value acquired from TBR - this indicates the exception
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setlos #~TBR_TT,gr2
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and.p gr20,gr2,gr20
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setlos #TBR_TT_BREAK,gr2
|
|
or.p gr20,gr2,gr20
|
|
|
|
# fudge PSR.PS and BPSR.BS to return to kernel mode through the trap
|
|
# table as trap 126
|
|
andi gr22,#~PSR_PS,gr22 /* PSR.PS should be 0 */
|
|
movgs gr22,psr
|
|
|
|
setlos #BPSR_BS,gr2 /* BPSR.BS should be 1 and BPSR.BET 0 */
|
|
movgs gr2,bpsr
|
|
|
|
# return through remainder of the exception prologue
|
|
# - need to load gr23 with return handler address
|
|
sethi.p %hi(__entry_return_from_user_exception),gr23
|
|
setlo %lo(__entry_return_from_user_exception),gr23
|
|
sethi.p %hi(__entry_common),gr3
|
|
setlo %lo(__entry_common),gr3
|
|
movgs gr3,bpcsr
|
|
|
|
LEDS 0x301f,gr2
|
|
|
|
ldi @(gr31,#REG_CCR),gr3
|
|
movgs gr3,ccr
|
|
lddi.p @(gr31,#REG_GR(2)),gr2
|
|
xor gr31,gr31,gr31
|
|
movgs gr0,brr
|
|
#ifdef CONFIG_MMU
|
|
movsg scr3,gr31
|
|
#endif
|
|
rett #1
|
|
|
|
###############################################################################
|
|
#
|
|
# resume normal debug-mode entry
|
|
#
|
|
###############################################################################
|
|
__break_continue:
|
|
LEDS 0x4003,gr2
|
|
|
|
# set up the kernel stack pointer
|
|
sti sp,@(gr31,#REG_SP)
|
|
|
|
sethi.p %hi(__break_stack_tos),sp
|
|
setlo %lo(__break_stack_tos),sp
|
|
|
|
# finish building the exception frame
|
|
stdi gr4 ,@(gr31,#REG_GR(4))
|
|
stdi gr6 ,@(gr31,#REG_GR(6))
|
|
stdi gr8 ,@(gr31,#REG_GR(8))
|
|
stdi gr10,@(gr31,#REG_GR(10))
|
|
stdi gr12,@(gr31,#REG_GR(12))
|
|
stdi gr14,@(gr31,#REG_GR(14))
|
|
stdi gr16,@(gr31,#REG_GR(16))
|
|
stdi gr18,@(gr31,#REG_GR(18))
|
|
stdi gr20,@(gr31,#REG_GR(20))
|
|
stdi gr22,@(gr31,#REG_GR(22))
|
|
stdi gr24,@(gr31,#REG_GR(24))
|
|
stdi gr26,@(gr31,#REG_GR(26))
|
|
sti gr0 ,@(gr31,#REG_GR(28)) /* NULL frame pointer */
|
|
sti gr29,@(gr31,#REG_GR(29))
|
|
sti gr30,@(gr31,#REG_GR(30))
|
|
sti gr8 ,@(gr31,#REG_ORIG_GR8)
|
|
|
|
#ifdef CONFIG_MMU
|
|
movsg scr3,gr19
|
|
sti gr19,@(gr31,#REG_GR(31))
|
|
#endif
|
|
|
|
movsg bpsr ,gr19
|
|
movsg tbr ,gr20
|
|
movsg bpcsr,gr21
|
|
movsg psr ,gr22
|
|
movsg isr ,gr23
|
|
movsg cccr ,gr25
|
|
movsg lr ,gr26
|
|
movsg lcr ,gr27
|
|
|
|
andi.p gr22,#~(PSR_S|PSR_ET),gr5 /* rebuild PSR */
|
|
andi gr19,#PSR_ET,gr4
|
|
or.p gr4,gr5,gr5
|
|
srli gr19,#10,gr4
|
|
andi gr4,#PSR_S,gr4
|
|
or.p gr4,gr5,gr5
|
|
|
|
setlos #-1,gr6
|
|
sti gr20,@(gr31,#REG_TBR)
|
|
sti gr21,@(gr31,#REG_PC)
|
|
sti gr5 ,@(gr31,#REG_PSR)
|
|
sti gr23,@(gr31,#REG_ISR)
|
|
sti gr25,@(gr31,#REG_CCCR)
|
|
stdi gr26,@(gr31,#REG_LR)
|
|
sti gr6 ,@(gr31,#REG_SYSCALLNO)
|
|
|
|
# store CPU-specific regs
|
|
movsg iacc0h,gr4
|
|
movsg iacc0l,gr5
|
|
stdi gr4,@(gr31,#REG_IACC0)
|
|
|
|
movsg gner0,gr4
|
|
movsg gner1,gr5
|
|
stdi gr4,@(gr31,#REG_GNER0)
|
|
|
|
# build the debug register frame
|
|
movsg brr,gr4
|
|
movgs gr0,brr
|
|
movsg nmar,gr5
|
|
movsg dcr,gr6
|
|
|
|
stdi gr4 ,@(gr31,#REG_BRR)
|
|
sti gr19,@(gr31,#REG_BPSR)
|
|
sti.p gr6 ,@(gr31,#REG_DCR)
|
|
|
|
# trap exceptions during break handling and disable h/w breakpoints/watchpoints
|
|
sethi %hi(DCR_EBE),gr5
|
|
setlo.p %lo(DCR_EBE),gr5
|
|
sethi %hi(__entry_breaktrap_table),gr4
|
|
setlo %lo(__entry_breaktrap_table),gr4
|
|
movgs gr5,dcr
|
|
movgs gr4,tbr
|
|
|
|
# set up kernel global registers
|
|
sethi.p %hi(__kernel_current_task),gr5
|
|
setlo %lo(__kernel_current_task),gr5
|
|
ld @(gr5,gr0),gr29
|
|
ldi.p @(gr29,#4),gr15 ; __current_thread_info = current->thread_info
|
|
|
|
sethi %hi(_gp),gr16
|
|
setlo.p %lo(_gp),gr16
|
|
|
|
# make sure we (the kernel) get div-zero and misalignment exceptions
|
|
setlos #ISR_EDE|ISR_DTT_DIVBYZERO|ISR_EMAM_EXCEPTION,gr5
|
|
movgs gr5,isr
|
|
|
|
# enter the GDB stub
|
|
LEDS 0x4007,gr2
|
|
|
|
or.p gr0,gr0,fp
|
|
call debug_stub
|
|
|
|
LEDS 0x403f,gr2
|
|
|
|
# return from break
|
|
lddi @(gr31,#REG_IACC0),gr4
|
|
movgs gr4,iacc0h
|
|
movgs gr5,iacc0l
|
|
|
|
lddi @(gr31,#REG_GNER0),gr4
|
|
movgs gr4,gner0
|
|
movgs gr5,gner1
|
|
|
|
lddi @(gr31,#REG_LR) ,gr26
|
|
lddi @(gr31,#REG_CCR) ,gr24
|
|
lddi @(gr31,#REG_PSR) ,gr22
|
|
ldi @(gr31,#REG_PC) ,gr21
|
|
ldi @(gr31,#REG_TBR) ,gr20
|
|
ldi.p @(gr31,#REG_DCR) ,gr6
|
|
|
|
andi gr22,#PSR_S,gr19 /* rebuild BPSR */
|
|
andi.p gr22,#PSR_ET,gr5
|
|
slli gr19,#10,gr19
|
|
or gr5,gr19,gr19
|
|
|
|
movgs gr6 ,dcr
|
|
movgs gr19,bpsr
|
|
movgs gr20,tbr
|
|
movgs gr21,bpcsr
|
|
movgs gr23,isr
|
|
movgs gr24,ccr
|
|
movgs gr25,cccr
|
|
movgs gr26,lr
|
|
movgs gr27,lcr
|
|
|
|
LEDS 0x407f,gr2
|
|
|
|
#ifdef CONFIG_MMU
|
|
ldi @(gr31,#REG_GR(31)),gr2
|
|
movgs gr2,scr3
|
|
#endif
|
|
|
|
ldi @(gr31,#REG_GR(30)),gr30
|
|
ldi @(gr31,#REG_GR(29)),gr29
|
|
lddi @(gr31,#REG_GR(26)),gr26
|
|
lddi @(gr31,#REG_GR(24)),gr24
|
|
lddi @(gr31,#REG_GR(22)),gr22
|
|
lddi @(gr31,#REG_GR(20)),gr20
|
|
lddi @(gr31,#REG_GR(18)),gr18
|
|
lddi @(gr31,#REG_GR(16)),gr16
|
|
lddi @(gr31,#REG_GR(14)),gr14
|
|
lddi @(gr31,#REG_GR(12)),gr12
|
|
lddi @(gr31,#REG_GR(10)),gr10
|
|
lddi @(gr31,#REG_GR(8)) ,gr8
|
|
lddi @(gr31,#REG_GR(6)) ,gr6
|
|
lddi @(gr31,#REG_GR(4)) ,gr4
|
|
lddi @(gr31,#REG_GR(2)) ,gr2
|
|
ldi.p @(gr31,#REG_SP) ,sp
|
|
|
|
xor gr31,gr31,gr31
|
|
movgs gr0,brr
|
|
#ifdef CONFIG_MMU
|
|
movsg scr3,gr31
|
|
#endif
|
|
rett #1
|
|
|
|
###################################################################################################
|
|
#
|
|
# GDB stub "system calls"
|
|
#
|
|
###################################################################################################
|
|
|
|
#ifdef CONFIG_GDBSTUB
|
|
# void gdbstub_console_write(struct console *con, const char *p, unsigned n)
|
|
.globl gdbstub_console_write
|
|
gdbstub_console_write:
|
|
break
|
|
bralr
|
|
#endif
|
|
|
|
# GDB stub BUG() trap
|
|
# GR8 is the proposed signal number
|
|
.globl __debug_bug_trap
|
|
__debug_bug_trap:
|
|
break
|
|
bralr
|
|
|
|
# transfer kernel exeception to GDB for handling
|
|
.globl __break_hijack_kernel_event
|
|
__break_hijack_kernel_event:
|
|
break
|
|
.globl __break_hijack_kernel_event_breaks_here
|
|
__break_hijack_kernel_event_breaks_here:
|
|
nop
|
|
|
|
#ifdef CONFIG_MMU
|
|
# handle a return from TLB-miss that requires single-step reactivation
|
|
.globl __break_tlb_miss_return_break
|
|
__break_tlb_miss_return_break:
|
|
break
|
|
__break_tlb_miss_return_breaks_here:
|
|
nop
|
|
#endif
|
|
|
|
# guard the first .text label in the next file from confusion
|
|
nop
|