forked from luck/tmp_suning_uos_patched
d746286c1f
Since a number of powerpc chips are SoCs we end up having dma-able devices that are registered as platform or of_platform devices. We need to hook the archdata to setup proper dma_ops for these devices. Rather than having to add a bus_notify to each platform we add a default one at the highest priority (called first) to set the default dma_ops for of_platform and platform devices to dma_direct_ops. This allows platform code to override the ops by providing their own notifier call back. In the future to enable >4G DMA support on ppc32 we can hook swiotlb ops. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
142 lines
3.3 KiB
C
142 lines
3.3 KiB
C
/*
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* linux/arch/powerpc/platforms/cell/qpace_setup.c
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*
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* Copyright (C) 1995 Linus Torvalds
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* Adapted from 'alpha' version by Gary Thomas
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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* Modified by PPC64 Team, IBM Corp
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* Modified by Cell Team, IBM Deutschland Entwicklung GmbH
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* Modified by Benjamin Krill <ben@codiert.org>, IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/console.h>
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#include <linux/of_platform.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/kexec.h>
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#include <asm/pgtable.h>
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#include <asm/prom.h>
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#include <asm/rtas.h>
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#include <asm/dma.h>
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#include <asm/machdep.h>
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#include <asm/time.h>
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#include <asm/cputable.h>
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#include <asm/irq.h>
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#include <asm/spu.h>
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#include <asm/spu_priv1.h>
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#include <asm/udbg.h>
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#include <asm/cell-regs.h>
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#include "interrupt.h"
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#include "pervasive.h"
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#include "ras.h"
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#include "io-workarounds.h"
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static void qpace_show_cpuinfo(struct seq_file *m)
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{
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struct device_node *root;
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const char *model = "";
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root = of_find_node_by_path("/");
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if (root)
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model = of_get_property(root, "model", NULL);
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seq_printf(m, "machine\t\t: CHRP %s\n", model);
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of_node_put(root);
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}
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static void qpace_progress(char *s, unsigned short hex)
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{
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printk("*** %04x : %s\n", hex, s ? s : "");
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}
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static int __init qpace_publish_devices(void)
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{
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int node;
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/* Publish OF platform devices for southbridge IOs */
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of_platform_bus_probe(NULL, NULL, NULL);
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/* There is no device for the MIC memory controller, thus we create
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* a platform device for it to attach the EDAC driver to.
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*/
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for_each_online_node(node) {
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if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
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continue;
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platform_device_register_simple("cbe-mic", node, NULL, 0);
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}
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return 0;
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}
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machine_subsys_initcall(qpace, qpace_publish_devices);
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static void __init qpace_setup_arch(void)
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{
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#ifdef CONFIG_SPU_BASE
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spu_priv1_ops = &spu_priv1_mmio_ops;
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spu_management_ops = &spu_management_of_ops;
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#endif
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cbe_regs_init();
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#ifdef CONFIG_CBE_RAS
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cbe_ras_init();
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#endif
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#ifdef CONFIG_SMP
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smp_init_cell();
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#endif
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000;
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cbe_pervasive_init();
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#ifdef CONFIG_DUMMY_CONSOLE
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conswitchp = &dummy_con;
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#endif
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}
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static int __init qpace_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (!of_flat_dt_is_compatible(root, "IBM,QPACE"))
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return 0;
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hpte_init_native();
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return 1;
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}
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define_machine(qpace) {
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.name = "QPACE",
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.probe = qpace_probe,
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.setup_arch = qpace_setup_arch,
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.show_cpuinfo = qpace_show_cpuinfo,
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.restart = rtas_restart,
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.power_off = rtas_power_off,
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.halt = rtas_halt,
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.get_boot_time = rtas_get_boot_time,
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.get_rtc_time = rtas_get_rtc_time,
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.set_rtc_time = rtas_set_rtc_time,
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.calibrate_decr = generic_calibrate_decr,
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.progress = qpace_progress,
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.init_IRQ = iic_init_IRQ,
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#ifdef CONFIG_KEXEC
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.machine_kexec = default_machine_kexec,
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.machine_kexec_prepare = default_machine_kexec_prepare,
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.machine_crash_shutdown = default_machine_crash_shutdown,
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#endif
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};
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