forked from luck/tmp_suning_uos_patched
1618e84aa8
Since init_failed flag was moved to struct hda_intel, its access in the commit [4da63c6f: ALSA: hda - Fix broken PM due to incomplete i915 initialization] is also replaced with hda->init_failed appropriately.
399 lines
13 KiB
C
399 lines
13 KiB
C
/*
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* Common defines for the alsa driver code base for HD Audio.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __SOUND_HDA_PRIV_H
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#define __SOUND_HDA_PRIV_H
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#include <linux/clocksource.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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/*
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* registers
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*/
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#define AZX_REG_GCAP 0x00
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#define AZX_GCAP_64OK (1 << 0) /* 64bit address support */
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#define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */
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#define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */
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#define AZX_GCAP_ISS (15 << 8) /* # of input streams */
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#define AZX_GCAP_OSS (15 << 12) /* # of output streams */
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#define AZX_REG_VMIN 0x02
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#define AZX_REG_VMAJ 0x03
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#define AZX_REG_OUTPAY 0x04
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#define AZX_REG_INPAY 0x06
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#define AZX_REG_GCTL 0x08
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#define AZX_GCTL_RESET (1 << 0) /* controller reset */
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#define AZX_GCTL_FCNTRL (1 << 1) /* flush control */
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#define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
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#define AZX_REG_WAKEEN 0x0c
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#define AZX_REG_STATESTS 0x0e
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#define AZX_REG_GSTS 0x10
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#define AZX_GSTS_FSTS (1 << 1) /* flush status */
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#define AZX_REG_INTCTL 0x20
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#define AZX_REG_INTSTS 0x24
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#define AZX_REG_WALLCLK 0x30 /* 24Mhz source */
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#define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
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#define AZX_REG_SSYNC 0x38
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#define AZX_REG_CORBLBASE 0x40
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#define AZX_REG_CORBUBASE 0x44
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#define AZX_REG_CORBWP 0x48
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#define AZX_REG_CORBRP 0x4a
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#define AZX_CORBRP_RST (1 << 15) /* read pointer reset */
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#define AZX_REG_CORBCTL 0x4c
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#define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */
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#define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
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#define AZX_REG_CORBSTS 0x4d
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#define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */
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#define AZX_REG_CORBSIZE 0x4e
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#define AZX_REG_RIRBLBASE 0x50
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#define AZX_REG_RIRBUBASE 0x54
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#define AZX_REG_RIRBWP 0x58
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#define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */
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#define AZX_REG_RINTCNT 0x5a
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#define AZX_REG_RIRBCTL 0x5c
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#define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
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#define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */
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#define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
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#define AZX_REG_RIRBSTS 0x5d
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#define AZX_RBSTS_IRQ (1 << 0) /* response irq */
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#define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */
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#define AZX_REG_RIRBSIZE 0x5e
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#define AZX_REG_IC 0x60
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#define AZX_REG_IR 0x64
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#define AZX_REG_IRS 0x68
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#define AZX_IRS_VALID (1<<1)
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#define AZX_IRS_BUSY (1<<0)
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#define AZX_REG_DPLBASE 0x70
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#define AZX_REG_DPUBASE 0x74
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#define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */
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/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
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enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
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/* stream register offsets from stream base */
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#define AZX_REG_SD_CTL 0x00
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#define AZX_REG_SD_STS 0x03
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#define AZX_REG_SD_LPIB 0x04
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#define AZX_REG_SD_CBL 0x08
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#define AZX_REG_SD_LVI 0x0c
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#define AZX_REG_SD_FIFOW 0x0e
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#define AZX_REG_SD_FIFOSIZE 0x10
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#define AZX_REG_SD_FORMAT 0x12
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#define AZX_REG_SD_BDLPL 0x18
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#define AZX_REG_SD_BDLPU 0x1c
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/* PCI space */
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#define AZX_PCIREG_TCSEL 0x44
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/*
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* other constants
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*/
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/* max number of fragments - we may use more if allocating more pages for BDL */
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#define BDL_SIZE 4096
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#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
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#define AZX_MAX_FRAG 32
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/* max buffer size - no h/w limit, you can increase as you like */
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#define AZX_MAX_BUF_SIZE (1024*1024*1024)
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/* RIRB int mask: overrun[2], response[0] */
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#define RIRB_INT_RESPONSE 0x01
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#define RIRB_INT_OVERRUN 0x04
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#define RIRB_INT_MASK 0x05
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/* STATESTS int mask: S3,SD2,SD1,SD0 */
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#define AZX_MAX_CODECS 8
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#define AZX_DEFAULT_CODECS 4
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#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
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/* SD_CTL bits */
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#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
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#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
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#define SD_CTL_STRIPE (3 << 16) /* stripe control */
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#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
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#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
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#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
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#define SD_CTL_STREAM_TAG_SHIFT 20
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/* SD_CTL and SD_STS */
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#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
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#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
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#define SD_INT_COMPLETE 0x04 /* completion interrupt */
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#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
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SD_INT_COMPLETE)
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/* SD_STS */
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#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
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/* INTCTL and INTSTS */
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#define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */
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#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
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#define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
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/* below are so far hardcoded - should read registers in future */
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#define AZX_MAX_CORB_ENTRIES 256
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#define AZX_MAX_RIRB_ENTRIES 256
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/* driver quirks (capabilities) */
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/* bits 0-7 are used for indicating driver type */
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#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
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#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
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#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
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#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
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#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
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#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
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#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
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#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
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#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
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#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
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#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
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#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
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#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
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#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
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#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
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#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
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#define AZX_DCAPS_REVERSE_ASSIGN (1 << 24) /* Assign devices in reverse order */
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#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
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#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
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#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
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#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
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/* HD Audio class code */
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#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
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struct azx_dev {
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struct snd_dma_buffer bdl; /* BDL buffer */
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u32 *posbuf; /* position buffer pointer */
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unsigned int bufsize; /* size of the play buffer in bytes */
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unsigned int period_bytes; /* size of the period in bytes */
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unsigned int frags; /* number for period in the play buffer */
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unsigned int fifo_size; /* FIFO size */
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unsigned long start_wallclk; /* start + minimum wallclk */
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unsigned long period_wallclk; /* wallclk for period */
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void __iomem *sd_addr; /* stream descriptor pointer */
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u32 sd_int_sta_mask; /* stream int status mask */
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/* pcm support */
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struct snd_pcm_substream *substream; /* assigned substream,
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* set in PCM open
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*/
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unsigned int format_val; /* format value to be set in the
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* controller and the codec
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*/
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unsigned char stream_tag; /* assigned stream */
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unsigned char index; /* stream index */
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int assigned_key; /* last device# key assigned to */
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unsigned int opened:1;
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unsigned int running:1;
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unsigned int irq_pending:1;
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unsigned int prepared:1;
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unsigned int locked:1;
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/*
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* For VIA:
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* A flag to ensure DMA position is 0
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* when link position is not greater than FIFO size
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*/
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unsigned int insufficient:1;
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unsigned int wc_marked:1;
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unsigned int no_period_wakeup:1;
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struct timecounter azx_tc;
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struct cyclecounter azx_cc;
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int delay_negative_threshold;
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#ifdef CONFIG_SND_HDA_DSP_LOADER
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/* Allows dsp load to have sole access to the playback stream. */
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struct mutex dsp_mutex;
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#endif
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};
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/* CORB/RIRB */
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struct azx_rb {
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u32 *buf; /* CORB/RIRB buffer
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* Each CORB entry is 4byte, RIRB is 8byte
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*/
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dma_addr_t addr; /* physical address of CORB/RIRB buffer */
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/* for RIRB */
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unsigned short rp, wp; /* read/write pointers */
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int cmds[AZX_MAX_CODECS]; /* number of pending requests */
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u32 res[AZX_MAX_CODECS]; /* last read value */
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};
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struct azx;
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/* Functions to read/write to hda registers. */
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struct hda_controller_ops {
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/* Register Access */
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void (*reg_writel)(u32 value, u32 __iomem *addr);
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u32 (*reg_readl)(u32 __iomem *addr);
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void (*reg_writew)(u16 value, u16 __iomem *addr);
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u16 (*reg_readw)(u16 __iomem *addr);
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void (*reg_writeb)(u8 value, u8 __iomem *addr);
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u8 (*reg_readb)(u8 __iomem *addr);
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/* Disable msi if supported, PCI only */
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int (*disable_msi_reset_irq)(struct azx *);
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/* Allocation ops */
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int (*dma_alloc_pages)(struct azx *chip,
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int type,
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size_t size,
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struct snd_dma_buffer *buf);
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void (*dma_free_pages)(struct azx *chip, struct snd_dma_buffer *buf);
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int (*substream_alloc_pages)(struct azx *chip,
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struct snd_pcm_substream *substream,
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size_t size);
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int (*substream_free_pages)(struct azx *chip,
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struct snd_pcm_substream *substream);
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void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream,
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struct vm_area_struct *area);
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/* Check if current position is acceptable */
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int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
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};
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struct azx_pcm {
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struct azx *chip;
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struct snd_pcm *pcm;
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struct hda_codec *codec;
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struct hda_pcm_stream *hinfo[2];
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struct list_head list;
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};
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typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);
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typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos);
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struct azx {
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struct snd_card *card;
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struct pci_dev *pci;
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int dev_index;
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/* chip type specific */
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int driver_type;
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unsigned int driver_caps;
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int playback_streams;
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int playback_index_offset;
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int capture_streams;
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int capture_index_offset;
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int num_streams;
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const int *jackpoll_ms; /* per-card jack poll interval */
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/* Register interaction. */
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const struct hda_controller_ops *ops;
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/* position adjustment callbacks */
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azx_get_pos_callback_t get_position[2];
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azx_get_delay_callback_t get_delay[2];
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/* pci resources */
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unsigned long addr;
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void __iomem *remap_addr;
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int irq;
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/* locks */
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spinlock_t reg_lock;
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struct mutex open_mutex; /* Prevents concurrent open/close operations */
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/* streams (x num_streams) */
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struct azx_dev *azx_dev;
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/* PCM */
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struct list_head pcm_list; /* azx_pcm list */
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/* HD codec */
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unsigned short codec_mask;
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int codec_probe_mask; /* copied from probe_mask option */
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struct hda_bus *bus;
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unsigned int beep_mode;
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/* CORB/RIRB */
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struct azx_rb corb;
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struct azx_rb rirb;
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/* CORB/RIRB and position buffers */
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struct snd_dma_buffer rb;
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struct snd_dma_buffer posbuf;
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#ifdef CONFIG_SND_HDA_PATCH_LOADER
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const struct firmware *fw;
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#endif
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/* flags */
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const int *bdl_pos_adj;
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int poll_count;
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unsigned int running:1;
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unsigned int initialized:1;
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unsigned int single_cmd:1;
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unsigned int polling_mode:1;
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unsigned int msi:1;
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unsigned int probing:1; /* codec probing phase */
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unsigned int snoop:1;
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unsigned int align_buffer_size:1;
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unsigned int region_requested:1;
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unsigned int disabled:1; /* disabled by VGA-switcher */
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/* for debugging */
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unsigned int last_cmd[AZX_MAX_CODECS];
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/* reboot notifier (for mysterious hangup problem at power-down) */
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struct notifier_block reboot_notifier;
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#ifdef CONFIG_SND_HDA_DSP_LOADER
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struct azx_dev saved_azx_dev;
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#endif
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};
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#ifdef CONFIG_X86
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#define azx_snoop(chip) ((chip)->snoop)
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#else
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#define azx_snoop(chip) true
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#endif
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/*
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* macros for easy use
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*/
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#define azx_writel(chip, reg, value) \
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((chip)->ops->reg_writel(value, (chip)->remap_addr + AZX_REG_##reg))
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#define azx_readl(chip, reg) \
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((chip)->ops->reg_readl((chip)->remap_addr + AZX_REG_##reg))
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#define azx_writew(chip, reg, value) \
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((chip)->ops->reg_writew(value, (chip)->remap_addr + AZX_REG_##reg))
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#define azx_readw(chip, reg) \
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((chip)->ops->reg_readw((chip)->remap_addr + AZX_REG_##reg))
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#define azx_writeb(chip, reg, value) \
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((chip)->ops->reg_writeb(value, (chip)->remap_addr + AZX_REG_##reg))
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#define azx_readb(chip, reg) \
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((chip)->ops->reg_readb((chip)->remap_addr + AZX_REG_##reg))
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#define azx_sd_writel(chip, dev, reg, value) \
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((chip)->ops->reg_writel(value, (dev)->sd_addr + AZX_REG_##reg))
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#define azx_sd_readl(chip, dev, reg) \
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((chip)->ops->reg_readl((dev)->sd_addr + AZX_REG_##reg))
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#define azx_sd_writew(chip, dev, reg, value) \
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((chip)->ops->reg_writew(value, (dev)->sd_addr + AZX_REG_##reg))
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#define azx_sd_readw(chip, dev, reg) \
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((chip)->ops->reg_readw((dev)->sd_addr + AZX_REG_##reg))
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#define azx_sd_writeb(chip, dev, reg, value) \
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((chip)->ops->reg_writeb(value, (dev)->sd_addr + AZX_REG_##reg))
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#define azx_sd_readb(chip, dev, reg) \
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((chip)->ops->reg_readb((dev)->sd_addr + AZX_REG_##reg))
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#endif /* __SOUND_HDA_PRIV_H */
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