forked from luck/tmp_suning_uos_patched
37f8173dd8
Currently instrumentation of atomic primitives is done at the architecture
level, while composites or fallbacks are provided at the generic level.
The result is that there are no uninstrumented variants of the
fallbacks. Since there is now need of such variants to isolate text poke
from any form of instrumentation invert this ordering.
Doing this means moving the instrumentation into the generic code as
well as having (for now) two variants of the fallbacks.
Notes:
- the various *cond_read* primitives are not proper fallbacks
and got moved into linux/atomic.c. No arch_ variants are
generated because the base primitives smp_cond_load*()
are instrumented.
- once all architectures are moved over to arch_atomic_ one of the
fallback variants can be removed and some 2300 lines reclaimed.
- atomic_{read,set}*() are no longer double-instrumented
Reported-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lkml.kernel.org/r/20200505134058.769149955@linutronix.de
90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Atomic operations usable in machine independent code */
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#ifndef _LINUX_ATOMIC_H
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#define _LINUX_ATOMIC_H
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#include <linux/types.h>
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#include <asm/atomic.h>
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#include <asm/barrier.h>
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/*
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* Relaxed variants of xchg, cmpxchg and some atomic operations.
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*
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* We support four variants:
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*
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* - Fully ordered: The default implementation, no suffix required.
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* - Acquire: Provides ACQUIRE semantics, _acquire suffix.
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* - Release: Provides RELEASE semantics, _release suffix.
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* - Relaxed: No ordering guarantees, _relaxed suffix.
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*
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* For compound atomics performing both a load and a store, ACQUIRE
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* semantics apply only to the load and RELEASE semantics only to the
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* store portion of the operation. Note that a failed cmpxchg_acquire
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* does -not- imply any memory ordering constraints.
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*
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* See Documentation/memory-barriers.txt for ACQUIRE/RELEASE definitions.
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*/
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#define atomic_cond_read_acquire(v, c) smp_cond_load_acquire(&(v)->counter, (c))
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#define atomic_cond_read_relaxed(v, c) smp_cond_load_relaxed(&(v)->counter, (c))
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#define atomic64_cond_read_acquire(v, c) smp_cond_load_acquire(&(v)->counter, (c))
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#define atomic64_cond_read_relaxed(v, c) smp_cond_load_relaxed(&(v)->counter, (c))
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/*
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* The idea here is to build acquire/release variants by adding explicit
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* barriers on top of the relaxed variant. In the case where the relaxed
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* variant is already fully ordered, no additional barriers are needed.
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*
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* If an architecture overrides __atomic_acquire_fence() it will probably
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* want to define smp_mb__after_spinlock().
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*/
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#ifndef __atomic_acquire_fence
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#define __atomic_acquire_fence smp_mb__after_atomic
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#endif
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#ifndef __atomic_release_fence
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#define __atomic_release_fence smp_mb__before_atomic
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#endif
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#ifndef __atomic_pre_full_fence
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#define __atomic_pre_full_fence smp_mb__before_atomic
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#endif
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#ifndef __atomic_post_full_fence
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#define __atomic_post_full_fence smp_mb__after_atomic
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#endif
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#define __atomic_op_acquire(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret = op##_relaxed(args); \
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__atomic_acquire_fence(); \
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__ret; \
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})
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#define __atomic_op_release(op, args...) \
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({ \
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__atomic_release_fence(); \
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op##_relaxed(args); \
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})
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#define __atomic_op_fence(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret; \
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__atomic_pre_full_fence(); \
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__ret = op##_relaxed(args); \
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__atomic_post_full_fence(); \
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__ret; \
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})
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#ifdef ARCH_ATOMIC
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#include <linux/atomic-arch-fallback.h>
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#include <asm-generic/atomic-instrumented.h>
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#else
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#include <linux/atomic-fallback.h>
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#endif
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#include <asm-generic/atomic-long.h>
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#endif /* _LINUX_ATOMIC_H */
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