forked from luck/tmp_suning_uos_patched
422dcafe47
Lochnagar is an evaluation and development board for Cirrus Logic Smart CODEC and Amp devices. It allows the connection of most Cirrus Logic devices on mini-cards, as well as allowing connection of various application processor systems to provide a full evaluation platform. This driver supports the board controller chip on the Lochnagar board. Audio system topology, clocking and power can all be controlled through the Lochnagar controller chip, allowing the device under test to be used in a variety of possible use cases. As the Lochnagar is a fairly complex device this MFD driver allows the drivers for the various features to be bound in. Initially clocking, regulator and pinctrl will be added as these are necessary to configure the system. But in time at least audio and voltage/current monitoring will also be added. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
158 lines
7.7 KiB
C
158 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Lochnagar1 register definitions
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*
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* Copyright (c) 2017-2018 Cirrus Logic, Inc. and
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* Cirrus Logic International Semiconductor Ltd.
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*
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* Author: Charles Keepax <ckeepax@opensource.cirrus.com>
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*/
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#ifndef LOCHNAGAR1_REGISTERS_H
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#define LOCHNAGAR1_REGISTERS_H
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/* Register Addresses */
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#define LOCHNAGAR1_CDC_AIF1_SEL 0x0008
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#define LOCHNAGAR1_CDC_AIF2_SEL 0x0009
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#define LOCHNAGAR1_CDC_AIF3_SEL 0x000A
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#define LOCHNAGAR1_CDC_MCLK1_SEL 0x000B
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#define LOCHNAGAR1_CDC_MCLK2_SEL 0x000C
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#define LOCHNAGAR1_CDC_AIF_CTRL1 0x000D
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#define LOCHNAGAR1_CDC_AIF_CTRL2 0x000E
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#define LOCHNAGAR1_EXT_AIF_CTRL 0x000F
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#define LOCHNAGAR1_DSP_AIF1_SEL 0x0010
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#define LOCHNAGAR1_DSP_AIF2_SEL 0x0011
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#define LOCHNAGAR1_DSP_CLKIN_SEL 0x0012
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#define LOCHNAGAR1_DSP_AIF 0x0013
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#define LOCHNAGAR1_GF_AIF1 0x0014
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#define LOCHNAGAR1_GF_AIF2 0x0015
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#define LOCHNAGAR1_PSIA_AIF 0x0016
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#define LOCHNAGAR1_PSIA1_SEL 0x0017
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#define LOCHNAGAR1_PSIA2_SEL 0x0018
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#define LOCHNAGAR1_SPDIF_AIF_SEL 0x0019
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#define LOCHNAGAR1_GF_AIF3_SEL 0x001C
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#define LOCHNAGAR1_GF_AIF4_SEL 0x001D
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#define LOCHNAGAR1_GF_CLKOUT1_SEL 0x001E
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#define LOCHNAGAR1_GF_AIF1_SEL 0x001F
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#define LOCHNAGAR1_GF_AIF2_SEL 0x0020
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#define LOCHNAGAR1_GF_GPIO2 0x0026
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#define LOCHNAGAR1_GF_GPIO3 0x0027
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#define LOCHNAGAR1_GF_GPIO7 0x0028
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#define LOCHNAGAR1_RST 0x0029
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#define LOCHNAGAR1_LED1 0x002A
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#define LOCHNAGAR1_LED2 0x002B
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#define LOCHNAGAR1_I2C_CTRL 0x0046
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/*
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* (0x0008 - 0x000C, 0x0010 - 0x0012, 0x0017 - 0x0020)
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* CDC_AIF1_SEL - GF_AIF2_SEL
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*/
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#define LOCHNAGAR1_SRC_MASK 0xFF
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#define LOCHNAGAR1_SRC_SHIFT 0
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/* (0x000D) CDC_AIF_CTRL1 */
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#define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_MASK 0x40
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#define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_SHIFT 6
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#define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_MASK 0x20
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#define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_SHIFT 5
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#define LOCHNAGAR1_CDC_AIF2_ENA_MASK 0x10
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#define LOCHNAGAR1_CDC_AIF2_ENA_SHIFT 4
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#define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_MASK 0x04
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#define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_SHIFT 2
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#define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_MASK 0x02
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#define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_SHIFT 1
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#define LOCHNAGAR1_CDC_AIF1_ENA_MASK 0x01
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#define LOCHNAGAR1_CDC_AIF1_ENA_SHIFT 0
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/* (0x000E) CDC_AIF_CTRL2 */
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#define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_MASK 0x40
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#define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_SHIFT 6
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#define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_MASK 0x20
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#define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_SHIFT 5
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#define LOCHNAGAR1_CDC_AIF3_ENA_MASK 0x10
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#define LOCHNAGAR1_CDC_AIF3_ENA_SHIFT 4
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#define LOCHNAGAR1_CDC_MCLK1_ENA_MASK 0x02
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#define LOCHNAGAR1_CDC_MCLK1_ENA_SHIFT 1
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#define LOCHNAGAR1_CDC_MCLK2_ENA_MASK 0x01
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#define LOCHNAGAR1_CDC_MCLK2_ENA_SHIFT 0
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/* (0x000F) EXT_AIF_CTRL */
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#define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_MASK 0x20
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#define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_SHIFT 5
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#define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_MASK 0x10
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#define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_SHIFT 4
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#define LOCHNAGAR1_SPDIF_AIF_ENA_MASK 0x08
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#define LOCHNAGAR1_SPDIF_AIF_ENA_SHIFT 3
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/* (0x0013) DSP_AIF */
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#define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_MASK 0x40
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#define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_SHIFT 6
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#define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_MASK 0x20
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#define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_SHIFT 5
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#define LOCHNAGAR1_DSP_AIF2_ENA_MASK 0x10
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#define LOCHNAGAR1_DSP_AIF2_ENA_SHIFT 4
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#define LOCHNAGAR1_DSP_CLKIN_ENA_MASK 0x08
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#define LOCHNAGAR1_DSP_CLKIN_ENA_SHIFT 3
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#define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_MASK 0x04
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#define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_SHIFT 2
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#define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_MASK 0x02
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#define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_SHIFT 1
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#define LOCHNAGAR1_DSP_AIF1_ENA_MASK 0x01
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#define LOCHNAGAR1_DSP_AIF1_ENA_SHIFT 0
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/* (0x0014) GF_AIF1 */
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#define LOCHNAGAR1_GF_CLKOUT1_ENA_MASK 0x40
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#define LOCHNAGAR1_GF_CLKOUT1_ENA_SHIFT 6
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#define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_MASK 0x20
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#define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_SHIFT 5
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#define LOCHNAGAR1_GF_AIF3_BCLK_DIR_MASK 0x10
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#define LOCHNAGAR1_GF_AIF3_BCLK_DIR_SHIFT 4
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#define LOCHNAGAR1_GF_AIF3_ENA_MASK 0x08
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#define LOCHNAGAR1_GF_AIF3_ENA_SHIFT 3
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#define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_MASK 0x04
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#define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_SHIFT 2
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#define LOCHNAGAR1_GF_AIF1_BCLK_DIR_MASK 0x02
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#define LOCHNAGAR1_GF_AIF1_BCLK_DIR_SHIFT 1
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#define LOCHNAGAR1_GF_AIF1_ENA_MASK 0x01
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#define LOCHNAGAR1_GF_AIF1_ENA_SHIFT 0
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/* (0x0015) GF_AIF2 */
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#define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_MASK 0x20
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#define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_SHIFT 5
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#define LOCHNAGAR1_GF_AIF4_BCLK_DIR_MASK 0x10
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#define LOCHNAGAR1_GF_AIF4_BCLK_DIR_SHIFT 4
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#define LOCHNAGAR1_GF_AIF4_ENA_MASK 0x08
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#define LOCHNAGAR1_GF_AIF4_ENA_SHIFT 3
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#define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_MASK 0x04
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#define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_SHIFT 2
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#define LOCHNAGAR1_GF_AIF2_BCLK_DIR_MASK 0x02
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#define LOCHNAGAR1_GF_AIF2_BCLK_DIR_SHIFT 1
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#define LOCHNAGAR1_GF_AIF2_ENA_MASK 0x01
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#define LOCHNAGAR1_GF_AIF2_ENA_SHIFT 0
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/* (0x0016) PSIA_AIF */
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#define LOCHNAGAR1_PSIA2_LRCLK_DIR_MASK 0x40
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#define LOCHNAGAR1_PSIA2_LRCLK_DIR_SHIFT 6
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#define LOCHNAGAR1_PSIA2_BCLK_DIR_MASK 0x20
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#define LOCHNAGAR1_PSIA2_BCLK_DIR_SHIFT 5
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#define LOCHNAGAR1_PSIA2_ENA_MASK 0x10
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#define LOCHNAGAR1_PSIA2_ENA_SHIFT 4
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#define LOCHNAGAR1_PSIA1_LRCLK_DIR_MASK 0x04
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#define LOCHNAGAR1_PSIA1_LRCLK_DIR_SHIFT 2
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#define LOCHNAGAR1_PSIA1_BCLK_DIR_MASK 0x02
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#define LOCHNAGAR1_PSIA1_BCLK_DIR_SHIFT 1
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#define LOCHNAGAR1_PSIA1_ENA_MASK 0x01
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#define LOCHNAGAR1_PSIA1_ENA_SHIFT 0
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/* (0x0029) RST */
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#define LOCHNAGAR1_DSP_RESET_MASK 0x02
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#define LOCHNAGAR1_DSP_RESET_SHIFT 1
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#define LOCHNAGAR1_CDC_RESET_MASK 0x01
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#define LOCHNAGAR1_CDC_RESET_SHIFT 0
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/* (0x0046) I2C_CTRL */
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#define LOCHNAGAR1_CDC_CIF_MODE_MASK 0x01
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#define LOCHNAGAR1_CDC_CIF_MODE_SHIFT 0
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#endif
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