Chen-Yu Tsai f101796966 clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6 ... The pll6 has a /4 output that is used as an input to the ahb mux clock. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>		2015-03-25 11:46:41 -07:00
..
clk-a10-hosc.c
clk-a20-gmac.c
clk-factors.c
clk-factors.h
clk-mod0.c
clk-sun6i-apb0-gates.c
clk-sun6i-apb0.c
clk-sun6i-ar100.c
clk-sun8i-apb0.c
clk-sun8i-mbus.c
clk-sun9i-core.c
clk-sun9i-mmc.c
clk-sunxi.c	clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6	2015-03-25 11:46:41 -07:00
clk-usb.c	clk: sunxi: Add support for sun9i A80 USB clocks and resets	2015-02-23 09:25:54 +01:00
Makefile