forked from luck/tmp_suning_uos_patched
0ee3b6f87d
futex_atomic_cmpxchg_inatomic() is simply the 32-bit implementation of user_atomic_cmpxchg_inatomic(), which in turn is simply a generalization of the original code in futex_atomic_cmpxchg_inatomic(). Use the newly generalized user_atomic_cmpxchg_inatomic() as the futex implementation, too. [ hpa: retain the inline in futex.h rather than changing it to a macro ] Signed-off-by: Qiaowei Ren <qiaowei.ren@intel.com> Link: http://lkml.kernel.org/r/1387002303-6620-2-git-send-email-qiaowei.ren@intel.com Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
118 lines
2.8 KiB
C
118 lines
2.8 KiB
C
#ifndef _ASM_X86_FUTEX_H
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#define _ASM_X86_FUTEX_H
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#ifdef __KERNEL__
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/asm.h>
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#include <asm/errno.h>
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#include <asm/processor.h>
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#include <asm/smap.h>
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#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \
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asm volatile("\t" ASM_STAC "\n" \
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"1:\t" insn "\n" \
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"2:\t" ASM_CLAC "\n" \
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"\t.section .fixup,\"ax\"\n" \
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"3:\tmov\t%3, %1\n" \
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"\tjmp\t2b\n" \
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"\t.previous\n" \
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_ASM_EXTABLE(1b, 3b) \
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: "=r" (oldval), "=r" (ret), "+m" (*uaddr) \
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: "i" (-EFAULT), "0" (oparg), "1" (0))
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#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \
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asm volatile("\t" ASM_STAC "\n" \
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"1:\tmovl %2, %0\n" \
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"\tmovl\t%0, %3\n" \
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"\t" insn "\n" \
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"2:\t" LOCK_PREFIX "cmpxchgl %3, %2\n" \
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"\tjnz\t1b\n" \
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"3:\t" ASM_CLAC "\n" \
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"\t.section .fixup,\"ax\"\n" \
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"4:\tmov\t%5, %1\n" \
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"\tjmp\t3b\n" \
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"\t.previous\n" \
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_ASM_EXTABLE(1b, 4b) \
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_ASM_EXTABLE(2b, 4b) \
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: "=&a" (oldval), "=&r" (ret), \
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"+m" (*uaddr), "=&r" (tem) \
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: "r" (oparg), "i" (-EFAULT), "1" (0))
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static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
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{
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int op = (encoded_op >> 28) & 7;
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int cmp = (encoded_op >> 24) & 15;
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int oparg = (encoded_op << 8) >> 20;
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int cmparg = (encoded_op << 20) >> 20;
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int oldval = 0, ret, tem;
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if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
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oparg = 1 << oparg;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op1("xchgl %0, %2", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op1(LOCK_PREFIX "xaddl %0, %2", ret, oldval,
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uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op2("orl %4, %3", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op2("andl %4, %3", ret, oldval, uaddr, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op2("xorl %4, %3", ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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if (!ret) {
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switch (cmp) {
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case FUTEX_OP_CMP_EQ:
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ret = (oldval == cmparg);
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break;
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case FUTEX_OP_CMP_NE:
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ret = (oldval != cmparg);
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break;
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case FUTEX_OP_CMP_LT:
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ret = (oldval < cmparg);
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break;
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case FUTEX_OP_CMP_GE:
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ret = (oldval >= cmparg);
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break;
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case FUTEX_OP_CMP_LE:
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ret = (oldval <= cmparg);
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break;
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case FUTEX_OP_CMP_GT:
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ret = (oldval > cmparg);
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break;
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default:
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ret = -ENOSYS;
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}
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}
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return ret;
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}
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static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 newval)
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{
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return user_atomic_cmpxchg_inatomic(uval, uaddr, oldval, newval);
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}
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#endif
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#endif /* _ASM_X86_FUTEX_H */
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