forked from luck/tmp_suning_uos_patched
7911d3f7af
We currently allow any process to use rdpmc. This significantly weakens the protection offered by PR_TSC_DISABLED, and it could be helpful to users attempting to exploit timing attacks. Since we can't enable access to individual counters, use a very coarse heuristic to limit access to rdpmc: allow access only when a perf_event is mmapped. This protects seccomp sandboxes. There is plenty of room to further tighen these restrictions. For example, this allows rdpmc for any x86_pmu event, but it's only useful for self-monitoring tasks. As a side effect, cap_user_rdpmc will now be false for AMD uncore events. This isn't a real regression, since .event_idx is disabled for these events anyway for the time being. Whenever that gets re-added, the cap_user_rdpmc code can be adjusted or refactored accordingly. Signed-off-by: Andy Lutomirski <luto@amacapital.net> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Kees Cook <keescook@chromium.org> Cc: Andrea Arcangeli <aarcange@redhat.com> Cc: Vince Weaver <vince@deater.net> Cc: "hillf.zj" <hillf.zj@alibaba-inc.com> Cc: Valdis Kletnieks <Valdis.Kletnieks@vt.edu> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: http://lkml.kernel.org/r/a2bdb3cf3a1d70c26980d7c6dddfbaa69f3182bf.1414190806.git.luto@amacapital.net Signed-off-by: Ingo Molnar <mingo@kernel.org>
35 lines
609 B
C
35 lines
609 B
C
#ifndef _ASM_X86_MMU_H
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#define _ASM_X86_MMU_H
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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/*
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* The x86 doesn't have a mmu context, but
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* we put the segment information here.
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*/
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typedef struct {
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void *ldt;
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int size;
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#ifdef CONFIG_X86_64
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/* True if mm supports a task running in 32 bit compatibility mode. */
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unsigned short ia32_compat;
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#endif
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struct mutex lock;
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void __user *vdso;
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atomic_t perf_rdpmc_allowed; /* nonzero if rdpmc is allowed */
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} mm_context_t;
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#ifdef CONFIG_SMP
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void leave_mm(int cpu);
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#else
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static inline void leave_mm(int cpu)
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{
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}
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#endif
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#endif /* _ASM_X86_MMU_H */
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