forked from luck/tmp_suning_uos_patched
85f90cf6ca
This uses the new EC driver framework in drivers/platform/olpc. The XO-1 and XO-1.5-specific code is still in arch/x86, but the generic stuff (including a new workqueue; no more running EC commands with IRQs disabled!) can be shared with other architectures. Signed-off-by: Andres Salomon <dilinger@queued.net> Acked-by: Paul Fox <pgf@laptop.org> Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
/* OLPC machine specific definitions */
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#ifndef _ASM_X86_OLPC_H
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#define _ASM_X86_OLPC_H
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#include <asm/geode.h>
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struct olpc_platform_t {
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int flags;
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uint32_t boardrev;
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int ecver;
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};
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#define OLPC_F_PRESENT 0x01
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#define OLPC_F_DCON 0x02
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#define OLPC_F_EC_WIDE_SCI 0x04
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#ifdef CONFIG_OLPC
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extern struct olpc_platform_t olpc_platform_info;
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/*
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* OLPC board IDs contain the major build number within the mask 0x0ff0,
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* and the minor build number within 0x000f. Pre-builds have a minor
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* number less than 8, and normal builds start at 8. For example, 0x0B10
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* is a PreB1, and 0x0C18 is a C1.
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*/
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static inline uint32_t olpc_board(uint8_t id)
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{
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return (id << 4) | 0x8;
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}
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static inline uint32_t olpc_board_pre(uint8_t id)
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{
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return id << 4;
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}
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static inline int machine_is_olpc(void)
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{
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return (olpc_platform_info.flags & OLPC_F_PRESENT) ? 1 : 0;
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}
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/*
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* The DCON is OLPC's Display Controller. It has a number of unique
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* features that we might want to take advantage of..
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*/
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static inline int olpc_has_dcon(void)
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{
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return (olpc_platform_info.flags & OLPC_F_DCON) ? 1 : 0;
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}
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/*
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* The "Mass Production" version of OLPC's XO is identified as being model
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* C2. During the prototype phase, the following models (in chronological
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* order) were created: A1, B1, B2, B3, B4, C1. The A1 through B2 models
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* were based on Geode GX CPUs, and models after that were based upon
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* Geode LX CPUs. There were also some hand-assembled models floating
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* around, referred to as PreB1, PreB2, etc.
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*/
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static inline int olpc_board_at_least(uint32_t rev)
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{
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return olpc_platform_info.boardrev >= rev;
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}
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extern void olpc_ec_wakeup_set(u16 value);
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extern void olpc_ec_wakeup_clear(u16 value);
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extern bool olpc_ec_wakeup_available(void);
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extern int olpc_ec_mask_write(u16 bits);
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extern int olpc_ec_sci_query(u16 *sci_value);
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#else
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static inline int machine_is_olpc(void)
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{
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return 0;
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}
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static inline int olpc_has_dcon(void)
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{
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return 0;
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}
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static inline void olpc_ec_wakeup_set(u16 value) { }
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static inline void olpc_ec_wakeup_clear(u16 value) { }
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static inline bool olpc_ec_wakeup_available(void)
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{
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return false;
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}
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#endif
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#ifdef CONFIG_OLPC_XO1_PM
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extern void do_olpc_suspend_lowlevel(void);
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extern void olpc_xo1_pm_wakeup_set(u16 value);
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extern void olpc_xo1_pm_wakeup_clear(u16 value);
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#endif
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extern int pci_olpc_init(void);
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/* SCI source values */
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#define EC_SCI_SRC_EMPTY 0x00
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#define EC_SCI_SRC_GAME 0x01
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#define EC_SCI_SRC_BATTERY 0x02
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#define EC_SCI_SRC_BATSOC 0x04
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#define EC_SCI_SRC_BATERR 0x08
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#define EC_SCI_SRC_EBOOK 0x10 /* XO-1 only */
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#define EC_SCI_SRC_WLAN 0x20 /* XO-1 only */
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#define EC_SCI_SRC_ACPWR 0x40
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#define EC_SCI_SRC_BATCRIT 0x80
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#define EC_SCI_SRC_GPWAKE 0x100 /* XO-1.5 only */
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#define EC_SCI_SRC_ALL 0x1FF
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/* GPIO assignments */
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#define OLPC_GPIO_MIC_AC 1
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#define OLPC_GPIO_DCON_STAT0 5
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#define OLPC_GPIO_DCON_STAT1 6
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#define OLPC_GPIO_DCON_IRQ 7
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#define OLPC_GPIO_THRM_ALRM geode_gpio(10)
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#define OLPC_GPIO_DCON_LOAD 11
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#define OLPC_GPIO_DCON_BLANK 12
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#define OLPC_GPIO_SMB_CLK 14
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#define OLPC_GPIO_SMB_DATA 15
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#define OLPC_GPIO_WORKAUX geode_gpio(24)
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#define OLPC_GPIO_LID 26
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#define OLPC_GPIO_ECSCI 27
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#endif /* _ASM_X86_OLPC_H */
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