forked from luck/tmp_suning_uos_patched
445959821f
This patch changes 24xx to use new register access, except for clock framework. Clock framework register access will get updates in the next patch. Note that board-*.c files change GPMC (General Purpose Memory Controller) access to use gpmc_cs_write_reg() instead of accessing the registers directly. The code also uses gpmc_fck instead of it's parent clock core_l3_ck for GPMC clock. The H4 board file also adds h4_init_flash() function, which specify the flash start and end addresses. Also note that sleep.S removes some unused registers addresses. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
129 lines
4.1 KiB
ArmAsm
129 lines
4.1 KiB
ArmAsm
/*
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* linux/arch/arm/mach-omap2/sleep.S
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*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/arch/io.h>
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#include <asm/arch/pm.h>
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#include "sdrc.h"
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/* First address of reserved address space? apparently valid for OMAP2 & 3 */
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#define A_SDRC0_V (0xC0000000)
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.text
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/*
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* Forces OMAP into idle state
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*
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* omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
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* for normal idles.
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*
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* Note: This code get's copied to internal SRAM at boot. When the OMAP
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* wakes up it continues execution at the point it went to sleep.
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*/
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ENTRY(omap24xx_idle_loop_suspend)
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stmfd sp!, {r0, lr} @ save registers on stack
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mov r0, #0 @ clear for mcr setup
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mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
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ldmfd sp!, {r0, pc} @ restore regs and return
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ENTRY(omap24xx_idle_loop_suspend_sz)
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.word . - omap24xx_idle_loop_suspend
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/*
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* omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing
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* SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
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* SDRC.
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*
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* Input:
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* R0 : DLL ctrl value pre-Sleep
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* R1 : Processor+Revision
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* 2420: 0x21 = 242xES1, 0x26 = 242xES2.2
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* 2430: 0x31 = 2430ES1, 0x32 = 2430ES2
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*
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* The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
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* when we get called, but the DLL probably isn't. We will wait a bit more in
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* case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
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* if in unlocked mode.
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*
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* For less than 242x-ES2.2 upon wake from a sleep mode where the external
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* oscillator was stopped, a timing bug exists where a non-stabilized 12MHz
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* clock can pass into the PRCM can cause problems at DSP and IVA.
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* To work around this the code will switch to the 32kHz source prior to sleep.
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* Post sleep we will shift back to using the DPLL. Apparently,
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* CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait
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* 3x12MHz + 3x32kHz clocks for a full switch.
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*
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* The DLL load value is not kept in RETENTION or OFF. It needs to be restored
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* at wake
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*/
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ENTRY(omap24xx_cpu_suspend)
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stmfd sp!, {r0 - r12, lr} @ save registers on stack
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mov r3, #0x0 @ clear for mrc call
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mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
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nop
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nop
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ldr r3, A_SDRC_POWER @ addr of sdrc power
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ldr r4, [r3] @ value of sdrc power
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orr r4, r4, #0x40 @ enable self refresh on idle req
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mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
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str r4, [r3] @ make it so
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mov r2, #0
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nop
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mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
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nop
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loop:
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subs r5, r5, #0x1 @ awake, wait just a bit
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bne loop
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/* The DPLL has on before we take the DDR out of self refresh */
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bic r4, r4, #0x40 @ now clear self refresh bit.
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str r4, [r3] @ put vlaue back.
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ldr r4, A_SDRC0 @ make a clock happen
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ldr r4, [r4]
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nop @ start auto refresh only after clk ok
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movs r0, r0 @ see if DDR or SDR
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ldrne r1, A_SDRC_DLLA_CTRL_S @ get addr of DLL ctrl
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strne r0, [r1] @ rewrite DLLA to force DLL reload
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addne r1, r1, #0x8 @ move to DLLB
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strne r0, [r1] @ rewrite DLLB to force DLL reload
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mov r5, #0x1000
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loop2:
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subs r5, r5, #0x1
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bne loop2
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/* resume*/
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ldmfd sp!, {r0 - r12, pc} @ restore regs and return
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A_SDRC_POWER:
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.word OMAP242X_SDRC_REGADDR(SDRC_POWER)
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A_SDRC0:
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.word A_SDRC0_V
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A_SDRC_DLLA_CTRL_S:
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.word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
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ENTRY(omap24xx_cpu_suspend_sz)
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.word . - omap24xx_cpu_suspend
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